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| revision: 3.0 912-3000-016 october, 1997 opti ? 82C465MV/mva/mvb sin g le-chi p mixed volta g e notebook solution data book
opti inc. 888 tasman drive milpitas, ca 95035 tel: (408) 486-8000 fax: (408) 486-8001 www: http://www.opti.com/ ii cop y ri g ht copyri g ht ? 1997, opti inc. all ri g hts reserved. no part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any lan g ua g e or computer lan g ua g e, in any form or by any means, electronic, mechani- cal, ma g netic, optical, chemical, manual, or otherwise, without the prior written permission of opti incorporated, 888 tasman drive, milpitas, ca 95035. disclaimer opti inc. makes no representations or warranties with respect to the desi g n and documentation herein described and espe- cially disclaims any implied warranties of merchantability or fitness for any particular purpose. further, opti inc. reserves t he ri g ht to revise the desi g n and associated documentation and to make chan g es from time to time in the content without obli g ation of opti inc. to notify any person of such revisions or chan g es. note: before desi g nin g contact opti for latest product alerts, applications notes, and errata for this product line. trademarks opti and opti inc. are re g istered trademarks of opti inc. all other trademarks and copyri g hts are the property of their respec- tive holders. table of contents opti ? 912-3000-016 pa g e iii revision: 3.0 82C465MV/mva/mvb 1.0 features .................................................................................................................... ........ 1 2.0 overview .................................................................................................................... ....... 4 2.1 upgrade comparison .......................................................................................................... ...............4 3.0 signal definitions .......................................................................................................... ... 5 3.1 terminology/nomenclature conventions ........................................................................................ 5 3.2 pinout options .............................................................................................................. ......................5 3.3 strap-selected interface options ............................................................................................ ..........5 3.3.1 mixed volta g e interface options ............................................................................................7 3.3.2 resume reset ( rsmrst# ) function ....................................................................................7 3.3.3 readin g the 1x/2x strap settin g ............................................................................................7 3.3.4 usin g strap options with ttl lo g ic .......................................................................................8 3.4 program selected interface options.......................................................................................... .......9 3.4.1 dackmux decoder lines source ......................................................................................... 9 3.4.2 epmi si g nal source .............................................................................................................10 3.4.2.1 additional epmi sources ......................................................................................10 3.5 standard mode 82C465MV interface ............................................................................................ ...11 3.5.1 reduced memor y interface si g nal group option.................................................................12 3.5.2 82C465MV interface with l2 cache support .......................................................................14 3.5.3 82C465MV with 386 interface ..............................................................................................1 5 3.6 pin signal characteristics .................................................................................................. .............16 3.7 signal descriptions ......................................................................................................... .................21 3.7.1 clock and reset interface ................................................................................................. ...21 3.7.2 cpu / vl-bus interface .................................................................................................... ....22 3.7.3 dram interface ............................................................................................................ ........25 3.7.4 l2 cache interface ........................................................................................................ .......26 3.7.5 isa bus interface......................................................................................................... .........26 3.7.6 ipc ( 82c206 ) interface.........................................................................................................27 3.7.7 pmu interface............................................................................................................. ..........28 82C465MV/mva/mvb opti ? table of contents (cont.) pa g e iv 912-3000-016 revision: 3.0 3.7.8 miscellaneous si g nal interface.............................................................................................30 3.7.9 power and ground pins ..................................................................................................... ..31 4.0 functional description .................................................................................................. 33 4.1 463/465 chipset programming comparison ..................................................................................33 4.2 cpu and vl-bus interface .................................................................................................... ...........33 4.2.1 basic command interface ................................................................................................... .33 4.2.1.1 c y cle si g nals ........................................................................................................33 4.2.2 local device interface .................................................................................................... ......34 4.2.2.1 ldev# operation..................................................................................................34 4.2.2.2 lrdy# operation..................................................................................................35 4.2.2.3 vl-bus arbitration lo g ic .......................................................................................35 4.2.3 vl-bus masters ............................................................................................................ ........36 4.2.3.1 hardware considerations .....................................................................................36 4.2.3.2 pro g rammin g ........................................................................................................36 4.2.4 data bus conversion/data path lo g ic .................................................................................36 4.2.4.1 cpu data bus multiplex option ............................................................................36 4.2.5 numeric coprocessor interface............................................................................................3 7 4.2.5.1 hardware considerations .....................................................................................37 4.2.5.2 pro g rammin g ........................................................................................................37 4.2.6 special cpu interface support............................................................................................. 37 4.2.6.1 abilit y to cut cpu power durin g suspend ...........................................................37 4.2.6.2 pro g rammable a20m# functionalit y .....................................................................37 4.2.6.3 pro g rammable cpu reset functionalit y ............................................................38 4.2.6.4 pro g rammable dack2# functionalit y ..................................................................38 4.2.6.5 c y rix linear burst mode support ..........................................................................38 4.2.6.6 pro g rammable exclusion of coprocessor reco g nition.........................................38 4.2.6.7 pro g rammable rdyi# functionalit y ......................................................................38 4.3 system functions............................................................................................................ .................39 4.3.1 reset lo g ic...........................................................................................................................39 4.3.1.1 rst1#................................................................................................................... 39 4.3.1.2 rst4#................................................................................................................... 39 4.3.1.3 cpurst and sr eset.........................................................................................39 4.3.1.4 resume reset ( rsmrst# ) function...................................................................39 4.3.1.5 rapid reset generation.....................................................................................41 4.3.1.6 fast reset handlin g in smm ................................................................................41 82C465MV/mva/mvb opti ? table of contents (cont.) 912-3000-016 pa g e v revision: 3.0 4.3.2 s y stem clock generation.....................................................................................................42 4.3.2.1 input clocks ..........................................................................................................42 4.3.2.2 output clocks .......................................................................................................43 4.3.3 a20m# generation .......................................................................................................... .....45 4.3.3.1 rapid a20m# generation .....................................................................................45 4.3.3.2 inhibition of fast a20m# and fast reset generation ...........................................46 4.3.3.3 a20m# handlin g in smm ......................................................................................47 4.3.3.4 port 060/064h a20m# settin g accessibilit y ..........................................................47 4.4 dram controller ............................................................................................................. ..................48 4.4.1 dram controller hardware options ....................................................................................48 4.4.2 dram bus drive capabilit y ..................................................................................................50 4.4.3 settin g up dram operation ................................................................................................50 4.4.3.1 faster memor y c y cles ..........................................................................................52 4.4.3.2 dram mappin g scheme enable ..........................................................................52 4.4.3.3 dram control re g ister 2i - syscfg 35h ...........................................................52 4.4.4 edo dram support.......................................................................................................... ...53 4.4.5 dram c y cle speed..............................................................................................................53 4.4.6 s y stem rom and shadow ram ..........................................................................................54 4.5 cache control ............................................................................................................... ....................57 4.5.1 global enablin g of cacheabilit y ............................................................................................57 4.5.2 definin g non cacheable blocks ...........................................................................................57 4.5.2.1 c000, e000, f000h block cache enable .............................................................58 4.5.2.2 cache control of c000-f000h ..............................................................................59 4.5.2.3 cache invalidation feature ...................................................................................61 4.5.3 l1 write-back cache support ..............................................................................................6 1 4.5.3.1 hardware considerations .....................................................................................61 4.5.3.2 extra pro g rammable pin options .........................................................................62 4.5.3.3 pro g rammin g ........................................................................................................63 4.5.3.4 burst write feature...............................................................................................63 4.5.4 l2 cache support.......................................................................................................... .......64 4.5.4.1 performance .........................................................................................................65 4.5.4.2 l2 cache operation details ..................................................................................65 4.5.4.3 l2 cache arran g ement.........................................................................................67 4.5.4.4 differences between l2 support and no cache support modes .........................68 4.5.4.5 hardware considerations .....................................................................................69 4.5.4.6 pro g rammin g ........................................................................................................69 4.5.4.7 timin g control re g ister ........................................................................................70 82C465MV/mva/mvb opti ? table of contents (cont.) pa g e vi 912-3000-016 revision: 3.0 4.6 peripheral interface logic.................................................................................................. ..............71 4.6.1 isa bus lo g ic .......................................................................................................................71 4.6.1.1 hardware considerations .....................................................................................71 4.6.1.2 isa write c y cle inhibition .....................................................................................72 4.6.1.3 isa bus clock options..........................................................................................73 4.6.1.4 isa bus refresh control.......................................................................................73 4.6.1.5 pro g rammin g ........................................................................................................74 4.6.1.6 isa bus address buffer enable si g nal .................................................................75 4.6.1.7 dockin g station attachment feature ....................................................................75 4.6.2 pro g rammed hardware reset..............................................................................................76 4.6.3 inte g rated peripheral controller ...........................................................................................76 4.6.3.1 multiplexor hardware considerations ...................................................................76 4.6.3.2 dma hardware considerations ............................................................................76 4.6.3.3 ipc confi g uration pro g rammin g ...........................................................................77 4.6.3.4 interrupt controller re g ister pro g rammin g ...........................................................77 4.6.3.5 dma controller pro g rammin g re g isters...............................................................81 4.6.3.6 determinin g dma status before suspend............................................................84 4.6.3.7 dma re g ister read back provisions ...................................................................85 4.6.3.8 ldev# sense control...........................................................................................86 4.6.3.9 t y pe f dma support ............................................................................................86 4.6.3.10 timer pro g rammin g re g isters ..............................................................................87 4.6.3.11 writin g /readin g i/o port 070h ..............................................................................88 4.6.3.12 additional flopp y support.....................................................................................89 4.6.3.13 irq8 polarit y .........................................................................................................89 4.6.4 inte g rated local-bus enhanced ide interface .....................................................................90 4.6.4.1 hardware considerations .....................................................................................90 4.6.4.2 performance and power .......................................................................................91 4.6.4.3 si g nal connection.................................................................................................91 4.6.4.4 dbe ( tris ) polarit y ..............................................................................................91 4.6.4.5 pro g rammin g ........................................................................................................91 4.6.4.6 four-drive ide support ........................................................................................96 4.6.5 compact isa interface ..................................................................................................... ....98 4.6.5.1 cisa stop clock c y cle generation ......................................................................99 4.6.5.2 confi g uration c y cle generation............................................................................99 82C465MV/mva/mvb opti ? table of contents (cont.) 912-3000-016 pa g e vii revision: 3.0 4.6.5.3 driveback c y cle handlin g ...................................................................................100 4.7 power management unit ....................................................................................................... .........102 4.7.1 activit y monitorin g ..............................................................................................................102 4.7.1.1 timers .................................................................................................................1 02 4.7.1.2 events .................................................................................................................1 03 4.7.2 timers.................................................................................................................... .............103 4.7.2.1 time-out count and time-out smi......................................................................104 4.7.3 access events............................................................................................................. ....105 4.7.3.1 serial ( comx ) and parallel port ( lpt ) access ...................................................106 4.7.3.2 isa bus flopp y and hard drive access .............................................................106 4.7.3.3 inte g rated controller hard drive access ............................................................106 4.7.3.4 ke y board access ................................................................................................106 4.7.3.5 lcd controller access........................................................................................107 4.7.3.6 chip select generation ( csg ) access ...............................................................108 4.7.3.7 general purpose ( gnr ) access .........................................................................108 4.7.4 activit y trackin g .................................................................................................................111 4.7.5 reloadin g idle_timer .....................................................................................................112 4.7.6 external pmi events ....................................................................................................... ....112 4.7.6.1 suspend/resume pin .........................................................................................113 4.7.6.2 epmi si g nal relocation ......................................................................................113 4.7.6.3 pro g rammin g ......................................................................................................114 4.7.6.4 power mana g ement event status ......................................................................115 4.8 system management interrupt (smi) ........................................................................................... .116 4.8.1 smi presettin g for various cpu t y pe ................................................................................118 4.8.1.1 intel sl-enhanced and amd 5x86 cpu settin g s ...............................................119 4.8.1.2 c y rix cpu settin g s .............................................................................................119 4.8.1.3 amd 486dxlv / ibm blue li g htnin g cpu settin g s .........................................119 4.8.1.4 non-smi cpu settin g s .......................................................................................120 4.8.2 loadin g initial smm code and data...................................................................................120 4.8.2.1 smbase re g ister...............................................................................................121 4.8.3 run-time smi address relocation ....................................................................................122 4.8.3.1 relocation with standard interface smi..............................................................122 4.8.3.2 relocation with alternative interface smi ...........................................................122 4.8.4 smi event generation ...................................................................................................... ..122 4.8.4.1 time-out event generation of smi .....................................................................122 4.8.4.2 access event generation of smi ........................................................................122 4.8.4.3 no flush re q uired on entr y to smm ..................................................................123 82C465MV/mva/mvb opti ? table of contents (cont.) pa g e viii 912-3000-016 revision: 3.0 4.8.4.4 interrupt event generation of smi ......................................................................124 4.8.4.5 enablin g of events to generate smi...................................................................124 4.8.5 drq generation of smi ..................................................................................................... 126 4.8.6 servicin g an smi ................................................................................................................126 4.8.6.1 pmi source re g ister details...............................................................................127 4.8.6.2 epmi pin pmi sources .......................................................................................127 4.8.6.3 i/o smi trap indication .......................................................................................128 4.8.6.4 utilit y re g isters ...................................................................................................128 4.9 system power management ..................................................................................................... .....129 4.9.1 stpclk# mechanism to chan g e cpu speed...................................................................129 4.9.1.1 hardware considerations ...................................................................................129 4.9.1.2 pro g rammin g ......................................................................................................129 4.9.2 doze mode ................................................................................................................. ........131 4.9.2.1 dual doze timer reload selections ...................................................................131 4.9.2.2 presettin g events to reset doze mode ..............................................................133 4.9.2.3 ldev# doze reset.............................................................................................134 4.9.2.4 doze reset inside smm .....................................................................................134 4.9.2.5 automatic ( hardware ) doze mode......................................................................135 4.9.2.6 apm ( software ) doze mode ...............................................................................136 4.9.2.7 start doze bit......................................................................................................137 4.9.2.8 usin g doze time-out to tri gg er an smi .............................................................137 4.9.3 cpu thermal mana g ement unit ........................................................................................138 4.9.3.1 prediction of overtemp activit y ...........................................................................138 4.9.3.2 example ..............................................................................................................140 4.9.3.3 pro g rammin g ......................................................................................................140 4.9.4 emer g enc y overtemp sense .............................................................................................141 4.9.4.1 pro g rammin g ......................................................................................................141 4.10 suspend and resume ......................................................................................................... ...........142 4.10.1 suspend mode ............................................................................................................. ......142 4.10.1.1 suspend mode power savin g s...........................................................................143 4.10.2 resume event ............................................................................................................. .......145 4.10.2.1 epmi/irq events................................................................................................145 4.10.2.2 susp/rsm and ri events..................................................................................145 4.10.3 chip-level power conservation features..........................................................................147 4.10.3.1 automatic keeper resistors ...............................................................................147 4.10.3.2 zero-volt cpu suspend .....................................................................................148 4.10.3.3 clock stretchin g ..................................................................................................149 82C465MV/mva/mvb opti ? table of contents (cont.) 912-3000-016 pa g e ix revision: 3.0 4.10.3.4 stoppin g ipc clock when not in use ................................................................149 4.10.3.5 stoppin g kbclk and kbclk2 ...........................................................................149 4.11 power control latch and pio pins ........................................................................................... ....150 4.11.1 power control latch ...................................................................................................... .....150 4.11.1.1 hardware considerations ...................................................................................150 4.11.1.2 si g nal considerations .........................................................................................150 4.11.1.3 pro g rammin g ......................................................................................................150 4.11.2 pro g rammable i/o pins ......................................................................................................152 4.11.2.1 pio3/stpgnt# pin select .................................................................................152 4.11.2.2 pio2/cpuspd pin select...................................................................................152 4.11.2.3 pio1/nows# pin select ....................................................................................152 4.11.3 pro g rammable chip select feature ...................................................................................153 4.11.3.1 pro g rammable chip select limitations...............................................................155 5.0 register summary ....................................................................................................... 157 6.0 electrical ratings ......................................................................................................... 1 77 6.1 absolute maximum ratings.................................................................................................... .......177 6.2 5.0v dc characteristics: ta = 0c to +70c, vdds = 5.0v 5% .................................................177 6.3 3.3v dc characteristics: ta = 0c to +70c, vdd = 3.3v 5% ...................................................178 6.4 ac characteristics.......................................................................................................... ................178 6.5 timing characteristics: cpu interface = 3.3v, all other interfaces = 5.0v ................................179 6.5.1 cache timin g .....................................................................................................................179 6.5.2 dram timin g .....................................................................................................................179 6.5.3 at bus timin g ....................................................................................................................180 6.5.4 reset and local bus timin g ...............................................................................................181 6.5.5 power mana g ement timin g ................................................................................................182 6.6 timing diagrams............................................................................................................. ................183 6.7 functional memory timing diagrams........................................................................................... 205 6.7.1 fast pa g e mode ( fpm ) dram...........................................................................................205 6.7.2 extended data out ( edo ) ..................................................................................................213 82C465MV/mva/mvb opti ? table of contents (cont.) pa g e x 912-3000-016 revision: 3.0 7.0 test mode information ................................................................................................ 219 8.0 mechanical package outline....................................................................................... 221 a. incompatibilities with the 82c463mv ......................................................................... 223 a.1 power plane changes ......................................................................................................... ...........223 a.2 read cycle efficiency ....................................................................................................... .............223 a.3 ads# sampling ............................................................................................................... ................223 a.4 removal of sequencer ........................................................................................................ ...........223 a.5 default refresh rate change ................................................................................................. .......223 a.6 i/o blocking default change ................................................................................................. ........223 a.7 suspend mode dackmux parking...............................................................................................2 23 b. compact isa specification ......................................................................................... 225 b.1 compact isa overview ........................................................................................................ ..........225 b.2 compact isa cycle definition ................................................................................................ .......226 b.2.1 memor y c y cle.....................................................................................................................226 b.2.2 i/o c y cle............................................................................................................................ .229 b.2.3 dma on the cisa/isa bus .................................................................................................23 0 b.2.4 dack# c y cle......................................................................................................................230 b.2.5 confi g uration c y cle ............................................................................................................232 b.3 interrupt and dma request drive-back .......................................................................................2 34 b.3.1 interrupt re q uests ..............................................................................................................234 b.3.2 dma re q uests ...................................................................................................................234 b.4 performance control ......................................................................................................... .............235 b.5 compatibility and host responsibilities ..................................................................................... .236 b.6 shared speaker signal support (optional) ..................................................................................23 6 b.6.1 initial s y nchronization.........................................................................................................236 b.6.2 spkr sharin g durin g active mode ....................................................................................237 b.6.3 spkr sharin g durin g stop clock mode ............................................................................238 82C465MV/mva/mvb opti ? table of contents (cont.) 912-3000-016 pa g e xi revision: 3.0 b.6.4 audio output circuit recommendations ............................................................................238 b.7 automatic voltage threshold detection ......................................................................................2 38 c. 82c602a notebook companion chip......................................................................... 239 c.1 features.................................................................................................................... .......................239 c.1.1 general features.......................................................................................................... ......239 c.1.2 power-savin g features ......................................................................................................239 c.2 overview.................................................................................................................... ......................239 c.2.1 modes/chipset support ..................................................................................................... .239 c.2.2 desi g n notes ......................................................................................................................23 9 c.2.3 reducin g suspend power consumption............................................................................240 c.2.4 82c602a power consumption measurements ..................................................................240 c.2.5 internal real-time clock ( rtc ) .........................................................................................240 c.2.5.1 rtc features .....................................................................................................240 c.2.5.2 rtc overview.....................................................................................................241 c.2.5.3 rtc address map ..............................................................................................241 c.2.5.4 pro g rammin g the rtc ........................................................................................242 c.2.5.5 s q uare-wave output ...........................................................................................243 c.2.5.6 interrupts.............................................................................................................2 43 c.2.5.7 power-down/power-up c y cle ............................................................................248 c.2.5.8 control/status re g isters .....................................................................................249 c.3 signal definitions .......................................................................................................... .................251 c.3.1 486 nb mode si g nal descriptions......................................................................................254 c.3.1.1 clock and reset interface si g nals......................................................................254 c.3.1.2 interrupt/control interface si g nals ......................................................................254 c.3.1.3 isa dma arbiter interface si g nals......................................................................254 c.3.1.4 bus interface si g nals ..........................................................................................255 c.3.1.5 real-time clock and ke y board interface si g nals ..............................................255 c.3.1.6 miscellaneous interface si g nals .........................................................................256 c.3.1.7 power and ground pins ......................................................................................256 c.4 schematics.................................................................................................................. ....................257 c.5 82c602a mechanical package outline .........................................................................................2 58 82C465MV/mva/mvb opti ? table of contents (cont.) pa g e xii 912-3000-016 revision: 3.0 list of figures opti ? 912-3000-016 pa g e xiii revision: 3.0 82C465MV/mva/mvb fi g ure 1-1 s y stem block dia g ram ....................................................................................................................1 fi g ure 3-1 rst4# and buffer connection............................................................................................. ............8 fi g ure 3-2 standard dackmux0-2 connection ( syscfg a0h [ 3 ] = 1 ) ...........................................................9 fi g ure 3-3 multiplexed epmi input connections...................................................................................... .......10 fi g ure 3-4 pin dia g ram - standard mode .......................................................................................................11 fi g ure 3-5 pin dia g ram - 82c463mv-compatible mode ................................................................................13 fi g ure 3-6 pin dia g ram - 82C465MV interface with l2 cache support .........................................................14 fi g ure 3-7 pin dia g ram - 386 interface mode.................................................................................................15 fi g ure 4-1 resume reset function ................................................................................................... .............40 fi g ure 4-2 generation of hitm# and boff# ........................................................................................... ......61 fi g ure 4-3 l2 cache connection - two bank confi g uration...........................................................................64 fi g ure 4-4 correctin g aen for 16-bit dma......................................................................................................77 fi g ure 4-5 multiplexed input samplin g points ................................................................................................77 fi g ure 4-6 interface to inte g rated ide controller ............................................................................................90 fi g ure 4-7 activit y monitorin g block dia g ram ...............................................................................................102 fi g ure 4-8 thermal mana g ement block dia g ram .........................................................................................139 fi g ure 4-9 dampin g r-c for ppwrl spike ..................................................................................................150 fi g ure 6-1 rom c y cle with sdenh#, sdenl# ( l2 cache enabled ) ..........................................................183 fi g ure 6-2 isa bus c y cle............................................................................................................................ ..184 fi g ure 6-3 ke y board controller access c y cle ..............................................................................................185 fi g ure 6-4 cd [ 31:0 ] to sd [ 15:0 ] and mp [ 3:0 ] valid and invalid dela y ..........................................................185 fi g ure 6-5 sd [ 15:0 ] to cd [ 31:0 ] and mp [ 3:0 ] valid and invalid dela y ..........................................................185 fi g ure 6-6 data valid and invalid dela y between sd [ 15:8 ] and sd [ 7:0 ] data swappin g ............................186 fi g ure 6-7 nmi valid dela y related to iochk# ...........................................................................................186 fi g ure 6-8 l2 cache read miss - dirt y , double bank cache.......................................................................186 fi g ure 6-9 l2 cache write 0 wait state, not dirt y .......................................................................................187 fi g ure 6-10 l2 cache write, dirt y ..................................................................................................................187 fi g ure 6-11 l2 cache burst read 3-2-2-2 for double bank..........................................................................18 8 fi g ure 6-12 l2 cache burst read 3-2-2-2 for sin g le bank ...........................................................................189 fi g ure 6-13 l2 cache burst read 2-1-1-1 c y cle for double bank................................................................190 fi g ure 6-14 hitm# active with l2 cache hit, l2 cache 3-2-2-2 write c y cle ( cache 0 wait write ) .............191 fi g ure 6-15 hitm# si g nal active, burst write back c y cle, 1 wait state dram write setup ........................192 fi g ure 6-16 refresh c y cle ............................................................................................................................ ..193 fi g ure 6-17 dram burst read 5-4-4-4 ( pa g e hit ) .........................................................................................193 fi g ure 6-18 dram burst read x-2-2-2 ( pa g e miss ) ......................................................................................194 fi g ure 6-19 dram burst read 3-2-2-2 ( pa g e hit ) .........................................................................................194 fi g ure 6-20 dram burst read 4-3-3-3 ( pa g e hit ) .........................................................................................195 fi g ure 6-21 dram burst read x-3-3-3, 1 wait pa g e miss ............................................................................195 fi g ure 6-22 dram burst read x-3-3-3, 0 wait pa g e miss ............................................................................196 fi g ure 6-23 dram write wait state ( without l2 cache support ) ..................................................................196 82C465MV/mva/mvb opti ? list of figures (cont.) pa g e xiv 912-3000-016 revision: 3.0 fi g ure 6-24 sin g le local bus c y cle ................................................................................................................197 fi g ure 6-25 reset timin g ............................................................................................................................... 197 fi g ure 6-26 low word isa bus memor y read to hi g h word local bus with sdenl#, sdenh#, and sdir active......................................................................................................................... ..................198 fi g ure 6-27 write ppwr [ 3:0 ] with '1111' .......................................................................................................198 fi g ure 6-28 pio timin g example ( pio2 ) ........................................................................................................199 fi g ure 6-29 suspend se q uence after writin g '1' to syscfg 50h [ 0 ] ..............................................................200 fi g ure 6-30 resume se q uence ......................................................................................................................201 fi g ure 6-31 timer time-out and smi generation se q uence ..........................................................................202 fi g ure 6-32 apm stop clock se q uence .........................................................................................................203 fi g ure 6-33 doze se q uence .......................................................................................................................... .204 fi g ure 6-34 fpm dram, 3-2-2-2 pa g e hit read ...........................................................................................205 fi g ure 6-35 fpm dram, 5-2-2-2 inactive pa g e miss read ...........................................................................206 fi g ure 6-36 fpm dram, 8-2-2-2 active pa g e miss read..............................................................................206 fi g ure 6-37 fpm dram, 4-3-3-3 pa g e hit read ...........................................................................................207 fi g ure 6-38 fpm dram, 8-3-3-3 inactive pa g e miss read ...........................................................................207 fi g ure 6-39 fpm dram, 11-3-3-3 active pa g e miss read............................................................................208 fi g ure 6-40 fpm dram, 4-3-3-3 pa g e hit read ( 0 wait state pa g e miss ) ...................................................208 fi g ure 6-41 fpm dram, 6-3-3-3 inactive pa g e miss read ( 0 wait state pa g e miss ) ..................................209 fi g ure 6-42 fpm dram, 9-3-3-3 active pa g e miss read ( 0 wait state pa g e miss ) .....................................209 fi g ure 6-43 fpm dram, 5-4-4-4 pa g e hit read ...........................................................................................210 fi g ure 6-44 fpm dram, 8-4-4-4 inactive pa g e miss read ...........................................................................210 fi g ure 6-45 fpm dram, 12-4-4-4 active pa g e miss read............................................................................211 fi g ure 6-46 fpm dram, 0 wait state write ........................................................................................... .......211 fi g ure 6-47 fpm dram, 1 wait state write ........................................................................................... .......212 fi g ure 6-48 fpm dram, 5-2-2-2 inactive pa g e miss with ras 1/2 clk earl y ..............................................212 fi g ure 6-49 edo, 3-1-1-1 pa g e hit read.......................................................................................................213 fi g ure 6-50 edo, 5-1-1-1 inactive pa g e miss with ras 1/2 clk earl y .........................................................214 fi g ure 6-51 edo, 8-1-1-1 active pa g e miss with ras 1/2 clk earl y ............................................................214 fi g ure 6-52 edo, 10-1-1-1 active pa g e miss with normal ras ....................................................................215 fi g ure 6-53 edo, 3-2-2-2 pa g e hit read.......................................................................................................215 fi g ure 6-54 edo, 6-2-2-2 inactive pa g e miss ................................................................................................216 fi g ure 6-55 edo, 10-2-2-2 active pa g e miss read .......................................................................................216 fi g ure 6-56 edo, 4-2-2-2 pa g e hit read.......................................................................................................217 fi g ure 6-57 edo, 7-2-2-2 inactive pa g e miss ................................................................................................217 fi g ure 6-58 edo, 11-2-2-2 active pa g e miss.................................................................................................218 fi g ure 8-1 208-pin plastic quad flat pack ( qfp ) ........................................................................................221 fi g ure b-1 compact isa memor y c y cle operation, fast cisa timin g * .......................................................227 fi g ure b-2 compact isa memor y c y cle operation, standard isa timin g * ..................................................228 fi g ure b-3 compact isa i/o c y cle operation* .............................................................................................229 fi g ure b-4 compact isa dack# c y cle operation........................................................................................231 82C465MV/mva/mvb opti ? list of figures (cont.) 912-3000-016 pa g e xv revision: 3.0 fi g ure b-5 compact isa confi g uration c y cle operation ..............................................................................233 fi g ure b-6 compact isa interrupt and dma re q uest drive-back c y cle ......................................................235 fi g ure b-7 s y nchronizin g to atclk at 1st ale ............................................................................................236 fi g ure b-8 shared spkrout si g nal mana g ement......................................................................................237 fi g ure c-1 rtcvcc switchin g circuit example ...........................................................................................240 fi g ure c-1 rtc address map ......................................................................................................... ..............241 fi g ure c-1 update-ended/periodic interrupt relationship ............................................................................ 244 fi g ure c-2 quartz cr y stal e q uivalent circuit.................................................................................................245 fi g ure c-3 impedance graph......................................................................................................... ...............246 fi g ure c-4 rtc oscillator circuit block dia g ram..........................................................................................246 fi g ure c-5 t y pical temperature characteristics...........................................................................................247 fi g ure c-6 fre q uenc y variation versus load capacitance ..........................................................................248 fi g ure c-1 486 nb mode pin dia g ram ( 100-pin pqfp ) ...............................................................................251 fi g ure c-2 486 nb mode pin dia g ram ( 100-pin tqfp ) ................................................................................252 fi g ure c-1 82c602a internal circuitr y in 486 notebook mode .....................................................................257 fi g ure c-2 82c602a 100-pin plastic quad flat pack ( pqfp ) ......................................................................258 fi g ure c-3 82c602a 100-pin thin quad pack ( tqfp ) .................................................................................259 82C465MV/mva/mvb opti ? list of figures (cont.) pa g e xvi 912-3000-016 revision: 3.0 list of tables opti ? 912-3000-016 pa g e xvii revision: 3.0 82C465MV/mva/mvb table 3-1 si g nal definitions le g end................................................................................................................5 table 3-2 strap option summar y ....................................................................................................................6 table 3-3 strap settin g s for interface volta g es...............................................................................................7 table 3-4 1x/2x strappin g readback re g ister bit..........................................................................................7 table 3-5 pro g ram-selected dackmux interface recover y ..........................................................................9 table 3-6 dackmux interface option enablin g .............................................................................................9 table 3-7 pmimux multiplex option ............................................................................................... ..............10 table 3-8 epmmux multiplex option ............................................................................................... .............10 table 3-9 epmmux option enablin g ............................................................................................................10 table 3-10 strap-selected reduced memor y interface option .......................................................................12 table 3-11 82C465MV pin characteristics......................................................................................... .............16 table 4-1 product indicator re g ister bit........................................................................................................33 table 4-2 ads# samplin g control.................................................................................................................34 table 4-3 ldev# control......................................................................................................... ......................34 table 4-4 rdy# s y nchronization .................................................................................................................. 35 table 4-5 bus master enablin g .....................................................................................................................36 table 4-6 special cpu feature pro g rammin g bits .......................................................................................37 table 4-7 burst mode settin g ........................................................................................................................38 table 4-8 resume reset control .................................................................................................. ................39 table 4-9 s y stem control port a ( ps/2 compatibilit y port ) ...........................................................................41 table 4-10 controllin g fast reset ...................................................................................................................4 1 table 4-11 inhibition of sreset in smm.......................................................................................... ..............41 table 4-12 atclkin enablin g and sqwin fre q uenc y bits.............................................................................42 table 4-13 atclk rate selection................................................................................................. ..................43 table 4-14 recommended divisor settin g s for various input clock fre q uencies ..........................................44 table 4-15 at bus clock stretch controls ........................................................................................ ..............44 table 4-16 s y stem control port a ( ps/2 compatibilit y port ) ...........................................................................45 table 4-17 fast si g nal generation control bits ..............................................................................................46 table 4-18 a20m# read-onl y bit....................................................................................................................47 table 4-19 a20m# settin g within smm ...........................................................................................................47 table 4-20 s y mmetrical dram address decodin g .........................................................................................48 table 4-21 as y mmetrical dram decodin g , as y mmetr y syscfg d3h [ 4:0 ] = 0.............................................49 table 4-22 as y mmetrical dram decodin g , as y mmetr y syscfg d3h [ 4:0 ] = 1.............................................49 table 4-23 heav y -dut y memor y bus drive capabilit y feature........................................................................50 table 4-24 dram setup re g isters .................................................................................................................50 table 4-25 dram earl y ras# control ............................................................................................................52 table 4-26 edo dram selection ................................................................................................... ................53 table 4-27 su gg ested edo dram c y cle speed settin g s..............................................................................53 table 4-28 rom select re g isters ...................................................................................................................54 table 4-29 write destination re g isters ...........................................................................................................54 82C465MV/mva/mvb opti ? list of tables (cont.) pa g e xviii 912-3000-016 revision: 3.0 table 4-30 access control bit meanin g s for syscfg 38h [ 4:1 ] , 37h [ 7:4 ] , 31h [ 3:0 ] ........................................55 table 4-31 shadow ram control bits .............................................................................................. ...............55 table 4-32 write protect re g isters..................................................................................................................56 table 4-33 global cache control enable .......................................................................................... ..............57 table 4-34 size and valid start address bits of non-cacheable memor y blocks ..........................................57 table 4-35 non-cacheable block re g isters....................................................................................................57 table 4-36 c000, e000, f000h block cache enable ................................................................................. .....58 table 4-37 write-protected dram cache control ................................................................................... .......61 table 4-38 pin options .......................................................................................................... ..........................62 table 4-39 l1 writeback pro g rammin g bits ....................................................................................................63 table 4-40 burst write control .................................................................................................. ......................63 table 4-41 l2 cache support si g nal correspondence ...................................................................................65 table 4-42 correspondence between ta g bits and cpu address lines .......................................................66 table 4-43 maximum cacheable s y stem dram for each cache confi g uration ............................................66 table 4-44 sram speed re q uirements .........................................................................................................67 table 4-45 l2 cache arran g ement selection bit ............................................................................................67 table 4-46 l2 cache support option ( strap-selected ) ....................................................................................68 table 4-47 l2 cache re g isters .......................................................................................................................69 table 4-48 cache timin g control....................................................................................................................70 table 4-49 pin 186 function select.............................................................................................. ...................72 table 4-50 c y cle enable bits ................................................................................................................ ..........72 table 4-51 isa bus refresh control .............................................................................................. .................73 table 4-52 atclkin pro g rammin g re g ister bits ...........................................................................................73 table 4-53 peripheral device pro g rammin g re g ister bits ..............................................................................74 table 4-54 pio2 and sabufen# pro g ram bits..............................................................................................75 table 4-55 pro g rammed hardware reset bit..................................................................................................77 table 4-56 ipc confi g uration bits ................................................................................................................... 78 table 4-57 intc1 initialization command words ................................................................................... ........78 table 4-58 intc2 initialization command words ................................................................................... ........78 table 4-59 intc1 and intc2 operational command words .........................................................................80 table 4-60 interrupt controller shadow re g ister index values ......................................................................81 table 4-61 dma address and count re g isters...............................................................................................81 table 4-62 dma control and status re g ister .................................................................................................81 table 4-63 dmac1 control and status bits ........................................................................................ ............82 table 4-64 dmac2 control and status bits ........................................................................................ ............83 table 4-65 dma commands ......................................................................................................... ..................83 table 4-66 dma pro g ress bits ...................................................................................................................... ..84 table 4-67 ldev# samplin g for dma to local bus ........................................................................................86 table 4-68 t y pe f dma control............................................................................................................... .......86 table 4-69 timer control and status re g isters ..............................................................................................87 table 4-70 timer control bits................................................................................................... .......................87 82C465MV/mva/mvb opti ? list of tables (cont.) 912-3000-016 pa g e xix revision: 3.0 table 4-71 timer shadow re g isters ...............................................................................................................88 table 4-72 rtc index re g ister - i/o port 070h ..............................................................................................88 table 4-73 rtc index shadow re g ister .........................................................................................................88 table 4-74 flopp y shadow and control re g isters ..........................................................................................89 table 4-75 pmu control re g ister - syscfg 50h...........................................................................................89 table 4-76 ide controller confi g uration..........................................................................................................91 table 4-77 automatic c y cle settin g s available throu g h syscfg ach [ 7:4 ] ..................................................92 table 4-78 82C465MVa operation with primar y i/o ran g e selected ............................................................93 table 4-79 82C465MVa operation with secondar y i/o ran g e selected........................................................93 table 4-80 611 re g ister set ...................................................................................................................... ...94 table 4-81 82C465MVa operation with primar y i/o ran g e selected ............................................................96 table 4-82 82C465MVa operation with secondar y i/o ran g e selected........................................................96 table 4-83 82C465MVb operation with four drive support selected............................................................96 table 4-84 four drive ide control ............................................................................................... ...................97 table 4-85 compact isa control re g isters.....................................................................................................98 table 4-86 cisa c y cle generation re g isters ...............................................................................................100 table 4-87 timer control bits and clock source selection re g isters...........................................................103 table 4-88 time interval choices applicable to _timer settin g s ................................................................103 table 4-89 timer source re g isters ...............................................................................................................104 table 4-90 access events and their enablin g bit locations .....................................................................105 table 4-91 flopp y and hard drive dsk_access control ...........................................................................106 table 4-92 ide port address select bit.......................................................................................... ...............107 table 4-93 lcd controller access control........................................................................................ ............107 table 4-94 csg access control bits.............................................................................................. ...............108 table 4-95 general purpose access 1 re g isters..........................................................................................109 table 4-96 general purpose access 2 re g isters..........................................................................................109 table 4-97 memor y watchdo g feature extension re g isters ........................................................................110 table 4-98 memor y decodin g control bits....................................................................................................111 table 4-99 activit y trackin g re g isters ..........................................................................................................111 table 4-100 idle reload source re g isters ......................................................................................................112 table 4-101 external pmi source summar y ...................................................................................................112 table 4-102 epmi pro g rammin g re g isters .....................................................................................................114 table 4-103 power mana g ement event status ...............................................................................................115 table 4-104 irq and epmi smi sources ............................................................................................ ............116 table 4-105 time-out event smi sources.......................................................................................... .............117 table 4-106 access event smi sources ............................................................................................ .............117 table 4-107 smi initialization re g isters ..........................................................................................................118 table 4-108 bios code jump bit .................................................................................................. .................120 table 4-109 d y namic smi relocation bit ....................................................................................................... .120 table 4-110 software smi enable re g isters...................................................................................................121 table 4-111 smbase re g ister .......................................................................................................................121 82C465MV/mva/mvb opti ? list of tables (cont.) pa g e xx 912-3000-016 revision: 3.0 table 4-112 smi address relocation associated re g ister bits ......................................................................122 table 4-113 current and next access re g isters ............................................................................................123 table 4-114 smm flush control bits.............................................................................................. .................124 table 4-115 intrgrp irq select re g isters..................................................................................................125 table 4-116 smi event enable re g isters........................................................................................................125 table 4-117 dma trap related bits............................................................................................... .................126 table 4-118 smi service re g isters .................................................................................................................127 table 4-119 i/o access trap re g isters...........................................................................................................128 table 4-120 utilit y re g isters......................................................................................................................... ...128 table 4-121 re g ister bits associated with stpclk# feature ........................................................................130 table 4-122 doze time-out control re g isters ................................................................................................132 table 4-123 re g ister bits that select doze mode reset events ....................................................................133 table 4-124 local bus doze reset re g isters.................................................................................................134 table 4-125 doze reset bits inside and outside of smm ........................................................................... ...134 table 4-126 hardware doze mode re g isters .................................................................................................135 table 4-127 software doze mode re g isters...................................................................................................136 table 4-128 doze_timer smi generation bits ...................................................................................... ......137 table 4-129 power levels assi g ned to each operatin g mode .......................................................................138 table 4-130 thermal mana g ement re g isters .................................................................................................140 table 4-131 suspend control re g ister bits ....................................................................................................142 table 4-132 suspend mode power savin g feature bits.................................................................................143 table 4-133 suspend refresh pulse width control ................................................................................. .......144 table 4-134 resume event re g isters.............................................................................................................145 table 4-135 resume sources ( read-onl y) ....................................................................................................146 table 4-136 resistor control re g isters...........................................................................................................147 table 4-137 zero-volt cpu suspend re g ister bits.........................................................................................148 table 4-138 clock stretch re g ister.................................................................................................................149 table 4-139 pmu control re g ister - syscfg 50h.........................................................................................149 table 4-140 kbclk/kbclk2 stop control ........................................................................................... ..........149 table 4-141 ppwrl pro g rammin g re g isters .................................................................................................151 table 4-142 pio pin re g isters ........................................................................................................................1 52 table 4-143 pro g rammable chip select 0 re g isters ......................................................................................153 table 4-144 pro g rammable chip select 1 re g isters ......................................................................................154 table 4-145 pro g rammable chip select 2 re g isters ......................................................................................154 table 4-146 pro g rammable chip select 3 re g isters ......................................................................................155 table 5-1 syscfg re g ister space ............................................................................................................157 table b-1 compact isa ( cisa ) interface si g nals........................................................................................225 table b-2 common mad bit usa g e ............................................................................................................226 table b-3 mad bits durin g memor y c y cles ................................................................................................226 table b-4 mad bits durin g i/o c y cles ........................................................................................................229 table b-5 mad bits durin g dma acknowled g e c y cles...............................................................................230 82C465MV/mva/mvb opti ? list of tables (cont.) 912-3000-016 pa g e xxi revision: 3.0 table b-6 mad bits durin g stop clock confi g uration c y cles......................................................................232 table b-7 irq/drq drive back c y cle .........................................................................................................234 table b-8 spkr sharin g durin g active mode .............................................................................................237 table c-1 mode strappin g options..............................................................................................................239 table c-2 t y pical current consumption fi g ures for rtc power ................................................................240 table c-3 t y pical current consumption fi g ures for di g ital power..............................................................240 table c-4 time, alarm, and calendar formats..................................................................................... .......242 table c-5 s q uare-wave fre q uenc y /periodic interrupt rate........................................................................243 table c-6 cr y stal parameters ................................................................................................................ ......245 table c-7 control/status re g isters summar y .............................................................................................249 table c-8 re g isters a throu g h d bit formats..............................................................................................249 table c-9 486 nb mode - numerical pin cross-reference list ..................................................................253 82C465MV/mva/mvb opti ? list of tables (cont.) pa g e xxii 912-3000-016 revision: 3.0 82C465MV/mva/mvb single-chip mixed voltage notebook solution opti ? 912-3000-016 page 1 revision: 3.0 1.0 features cpu and vl-bus features the 82C465MV offers the followin g cpu interface features. ? supports amd?, c y rix?, intel?, and ibm? 486-t y pe 32-bit cpus, in 3.3v or 5.0v, includin g clock-tripled technolo gy . ? provides a fail-safe thermal mana g ement scheme that pre- dicts when cpu temperature is risin g to unsafe levels and forces the s y stem into a slower operatin g mode ( cool- down clockin g) . ? provides fast emulation of ke y board controller cpu reset and g ate a20 control; supports port 092h as well. ?full y supports local bus implementations, includin g vl-bus masters. ? offers complete microsoft? apm ( advance power man- a g ement ) operabilit y , with cpu stop clock support avail- able. ? supports next g eneration processor stop clock protocol, to take advanta g e of the performance improvement possible when pll start-up dela y is reduced from milliseconds to nanoseconds. ?en g a g es automatic internal resistors to eliminate the need for external pull-up / pull-down resistors on cpu address, data, and control lines. figure 1-1 system block diagram 486 cpu d[31:0] address bus control bus 1-64mb dram 2x ma[11:0] latch ppwr0 ppwr11 power control pins xd[7:0] sa[19:0] dma, irq opti sa[1:0] sd[15:0] isa control opti 208 pin pfp control d[31:0] address ma[11:0] a[23:2] 8 power management input pins 3x vesa local bus 82c602a bios rom ke y board controller sa[19:0] 82C465MV bus bus buffer (optional) d[31:0] address bus control bus 92c178 lcd svga ide isa bus 82C465MV/mva/mvb opti ? pa g e 2 912-3000-016 revision: 3.0 ? provides smbase relocation to match the feature found in some cpus that allows the smbase to be repro- g rammed; each 64kb se g ment can be remapped to an y 64kb-boundar y se g ment in the first 640kb of address space. ? offers pci compatibilit y in that the 82C465MV is full y com- patible with the opti 82c832 pci peripheral brid g e , pro- vidin g bus master support as well. ? with the core operatin g at 5.0v , runs as fast as 50mhz with: - cpu and isa bus i/o at 5.0v - cpu at 3.3v and isa bus i/o at 5.0v ? with the core operatin g at 3.3v , runs as fast as 40mhz with: - cpu and isa bus i/o at 3.3v dram/cache controller features the dram controller of the 82C465MV sin g le-chip note- book chipset runs from a 1x clock. it provides all of the per- formance features popular on powerful desktop s y stems and inte g rates power control for efficient operation. ? provides l1 cache support for an on-cpu writeback cache such as that found on the c y rix cx486dx/dx2 processor and l1 writeback cpus from intel and amd. ? provides power-mana g ed l2 cache support with a hi g h- performance , writeback external cache usin g the proven opti desktop 32-bit cache controller. inte g ral power con- trol turns on the chip select lines onl y to cache chips actu- all y bein g accessed , resultin g in extremel y low active- mode power consumption. moreover , the cache can be flushed and completel y turned off durin g low-power sus- pend mode. ? operates up to five banks of dram , supportin g an y mem- or y t y pe in an y bank , alon g with bank skippin g ( of interme- diate banks ) for automatic bios-based disablin g of defective dram. ? uses simplified memor y pro g rammin g scheme that sup- ports up to 12x12 s y mmetrical alon g with as y mmetrical dram such as 11x9 and 12x8 confi g urations. s y mmetri- cal and as y mmetrical t y pes can be mixed. ? allows an y bank to use 256kb , 512kb , 1mb , 2mb , 4mb , 8mb , or 16mb dram devices. ?pa g e mode dram controller supports 3-2-2-2 , 4-3-3-3 , and 5-4-4-4 burst read memor y c y cles , zero or one wait state dram write c y cles. ? supports two pro g rammable non-cacheable re g ions ?offers full y pro g rammable shadowin g of rom usin g dram in the c0000-fffffh re g ion. ? allows write-protected shadowin g and cachin g of s y stem and video bios. ? allows normal or slow refresh , cas-before-ras refresh , and self-refresh dram support; minimum-pulse refresh c y cles save power durin g suspend mode. isa bus features the isa bus interface of the 82C465MV chip offers man y improvements over previous g eneration opti notebook chipsets and competitive notebook chipsets. ? the internal 82c206 ipc offers a true sin g le-chip note- book implementation and is based on the proven 82c463mv core. ? the 82C465MV implements a complete isa-compatible s y stem with onl y one extra device , the opti 82c602 note- book companion chip , which contains a real time clock ( rtc ) with 256 b y tes of non-volatile ( backed up b y bat- ter y) ram and the e q uivalent of seven discrete ttl devices. ? the lo g ic inte g rates an enhanced ide interface runnin g at local-bus speeds ( 100% speed increase t y pical ) based on the proven opti 82c611 core. ?inte g ral ide support uses one external 74244 ttl device to control the ide , with a second 7416245 device optional for complete power-down isolation of the ide drive while the s y stem is active. dual drive support is also available. ? the ide command scheme shares no isa bus command lines , to prevent incompatibilit y with other isa bus devices due to ille g al short pulse c y cles on isa bus. ? 8.00mhz isa bus operation is available for implementa- tions re q uirin g exact adherence to the ori g inal isa stan- dard. ? 16-bit decodin g for internal i/o prevents conflicts for i/o peripherals addressed above 100h. ? four pro g rammable chip selects each decode ten address lines , a [ 9:0 ] for i/o addressin g or a [ 23:14 ] for memor y addressin g . memor y address decodin g allows simplified rom chip select g eneration for applications such as win- dows ce. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 3 revision: 3.0 power management features the s y ner g istic incorporation of power mana g ement and s y s- tem control features with the standard isa subs y stem con- troller of the 82C465MV chipset results in a compact desi g n that handles multiple tasks with a simple , common interface. the power mana g ement interrupt ( pmi ) scheme provides s y stem mana g ement code with a q uick means of identif y in g and handlin g events that affect power control and consump- tion. ?reco g nizes 28 separate pmi events. within these events , man y sub-events are also identifiable for a hi g h de g ree of power mana g ement monitorin g flexibilit y . ? eleven of the pmi events have individual timers to indicate inactivit y time-out situations. ?ei g ht external inputs are available for monitorin g as y n- chronous s y stem events. these are in addition to the isa- compatible irq lines that can also be monitored as power mana g ement events. ?pmi g eneration on access allows smi code to intercept status q ueries to powered-down devices that do not actu- all y need to be restarted simpl y to return an idle status. ? activit y trackin g re g ister of ei g ht events allows smi or non- smi applications a means of determinin g whether activit y has occurred since the last time the re g ister was checked. pollin g for i/o activit y can then be used instead of multiple smis for less si g nificant events. ? memor y watchdo g monitorin g allows accesses to memor y ran g es ( specified as pro g rammed ) to cause an smi. isa bus memor y devices that are not bein g accessed can be pro g rammed to cause a time-out smi so that unused peripherals can be powered down. ? supports s y stem-level low-power suspend , low-power suspend with zero-volt cpu suspend , or total s y stem zero-volt suspend ? twelve peripheral power control pins plus four user-defin- able i/o pins provides exceptional flexibilit y in peripheral device control. ? rtc alarm or modem rin g can wake up the s y stem from low-power suspend mode. ? suspend current leaka g e control ensures that ne g li g ible power will be consumed in suspend mode without addi- tional external bufferin g . backward compatibility features the 82C465MV is application-compatible with the 82c463mv for the vast ma j orit y of applications. ? the re g ister set and lo g ic are derived from and are a superset of the popular opti 82c463mv notebook chipset. ? when used as a drop-in replacement for the 82c463mv , the 82C465MV allows continued operation with no re q uired chan g es to the ori g inal 82c463mv bios. optional pro g rammin g needed to take advanta g e of per- formance improvements of 82C465MV lo g ic can be run from an executable file. ?man y of the new 82C465MV features can be utilized with onl y minor chan g es to the 82c463mv bios; more exten- sive use of the new feature set re q uires some chan g es to hardware desi g n as well. ? bios code need onl y check a sin g le re g ister to learn whether it is runnin g on the 82C465MV or on an 82c463/ 463mv chipset. note: the se q uencer of the 82c463mv has not been implemented in the 82C465MV. contact opti for information re g ardin g the conversion of se q uencer routines to smi routines. 82C465MV/mva/mvb opti ? pa g e 4 912-3000-016 revision: 3.0 2.0 overview the opti 82C465MV chipset is a hi g hl y inte g rated asic that implements 32-bit isa-compatible core lo g ic , alon g with power mana g ement and cpu thermal mana g ement hard- ware , in a sin g le device. its feature set provides an arra y of control and status monitorin g options , all accessed throu g h a simple and strai g htforward interface. all ma j or bios vendors provide power mana g ement modules that are optimized for the opti power mana g ement unit and provide extensive soft- ware hooks that allow s y stem desi g ners to inte g rate their own special features with minimal effort. the 82C465MV re q uires ver y little board space , implemented as a sin g le 208-pin pqfp packa g e in 0.6 micron ( 465mvb ) cmos technolo gy . it can be used in con j unction with a 100- pin buffer chip to completel y implement all the functions avail- able on a t y pical desktop s y stem. 2.1 upgrade comparison the 82C465MV chipset has been replaced b y the 82C465MVa and 82C465MVb derivatives. the followin g lists show the improvements made in each chip. note: this document covers the 82C465MV , 82C465MVa , and 82C465MVb. features that appl y onl y to the 82C465MVb are marked mvb , while features that appl y to both the 82C465MVa and the 82C465MVb are marked mva. unmarked features appl y to all three. mva ? no flush re q uired on entr y into smm ? dual doze timers ? local bus device can reset doze mode ? dma state can be full y saved and restored when suspend- in g ?dma can tri gg er smi ? hitm# and boff# can be connected directl y ( no external ttl ) ? fast reset and a20m# g eneration can be disabled ? i/o trap address is saved ? memor y watchdo g has additional control ? flopp y ports are shadowed ? isa bus address buffer can be disabled to save power ? the athold function is supported for dockin g station ? software can g enerate hard reset ?hi g h dram can be mode non-cacheable in l2 when usin g small ta g ram mvb ? edo dram is supported with no pin chan g es ? includes compact isa support for the 82c852 pcmcia controller ? isa bus refresh can be disabled to improve performance ? four ide drives are supported ?c y rix and amd 5x86 cpus are supported ?t y pe f dma is supported ? faster memor y c y cles are supported ? a20m# settin g can be restored inside smm ? suspend refresh can be a narrower pulse ? shadow ram is now cacheable in l1 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 5 revision: 3.0 3.0 signal definitions 3.1 terminology/nomenclature conventions the # s y mbol at the end of a si g nal name indicates that the active , or asserted state occurs when the si g nal is at a low volta g e level. when # is not present after the si g nal name , the si g nal is asserted when at the hi g h volta g e level. the terms assertion and ne g ation are used extensivel y . this is done to avoid confusion when workin g with a mixture of active low and active hi g h si g nals. the term assert , or assertion indicates that a si g nal is active , independent of whether that level is represented b y a hi g h or low volta g e. the term ne g ate , or ne g ation indicates that a si g nal is inactive. some pins have more than one function. these pins can be time-multiplexed , have strap options , or can be selected via re g ister pro g rammin g . included in the si g nal descriptions is a column titled selected b y which explains how to imple- ment/invoke the various functions that a pin ma y have. the tables in this section use several common abbreviations. table 3-1 lists the mnemonics and their meanin g s. note that ttl/cmos/schmitt-tri gg er levels pertain to inputs onl y . out- puts are driven at cmos levels. table 3-1 signal definitions legend 3.2 pinout options the opti 82C465MV can alter its character si g nificantl y b y simple strap options that are detected at hardware reset time. fi g ure 3-4 , fi g ure 3-5 , fi g ure 3-6 and fi g ure 3-7 , shown later in this section , illustrate the pinouts of the 82C465MV in the followin g modes: ? 82C465MV standard confi g uration without l2 cache interface ? 82c463mv-compatible confi g uration ? 82C465MV enhanced confi g uration with l2 cache interface ? 386 interface confi g uration ( blue li g htnin g -compatible ) . these modes are strap-selected interface options and are described below. 3.3 strap-selected interface options the flexibilit y of the 82C465MV across a wide variet y of appli- cations is due in lar g e part to its man y interface strap options. the options listed in table 3-2 are strap-selected at reset time as indicated. normall y, these pins are simpl y pulled up or down with a resistor to enable the desired function. the chip contains internal resistors that are enabled onl y at reset time to preset a default function , so that an external pull- up/pull-down ma y not be needed and can sometimes be avoided to save power. in most cases where an external resistor is re q uired , the direction ( pull-up or pull-down ) coin- cides with the inactive state of the si g nal and therefore con- sumes ne g li g ible power. the internal resistors have a value of approximatel y 50kohm. optionall y, the s y stem desi g ner can strap these pins with tristate drivers that enable their outputs onl y when the rst4# si g nal is active. the chip samples the lines on the risin g ed g e of the rst1# input , at which time rst4# is still active. each strap option is described in detail in the section of this document that describes the affected subs y stem. mnemonic description cmos cmos-level compatible dcdr decoder ext external g ground i input int internal i/o input/output mux multiplexer o output od open drain ppower pd pull-down resistor pu pull-up resistor sschmitt-tri gg er s/t/s sustain tristate ttl ttl-level compatible 82C465MV/mva/mvb opti ? pa g e 6 912-3000-016 revision: 3.0 * indicates that additional information is available on the followin g pa g es. ** indicates that heav y isa bus loadin g mi g ht re q uire use of external 4.7k pull-down resistors. the internal pull-down resistor ma y not be sufficient to oppose external conductance to vcc throu g h devices on the isa bus that have this line pulled up. table 3-2 strap option summary strap option signal pin no. control provided internal up/down at reset default with no strap l2 cache support sa0 146 strap sa0 low w/ 4.7k to enable l2 cache interface up no cache local-bus ide dbe polarit y tris# 176 strap dbe ( tris ) hi g h for active low , low for active hi g h up tris# active low ( for 82c463mv compatibilit y) input clock 1x/2x selection atcyc# 160 strap atcyc# hi g h for 1x w/10k down 2x clock oscclk ( for 82c463mv compatibilit y) fbclkout dela y ma11+ dackmux2 77 strap pin 77 hi g h for dela y w/10k down no dela y cpuclk dela y ras4#+ dackmux1 78 strap pin 78 low for dela y w/10k up no dela y new memor y control interface mdir+ dackmux0 79 strap pin 79 hi g h for old 82c463mv- compatible scheme w/10k down new interface sl-enhanced enable ccs1:0# 13 , 23 strap ccs0# and ccs1# hi g h for stpclk# operation w/10k down no stpclk# feature cpu clock 1x/2x selection * ccs2# 3 strap ccs2# hi g h for 2x clock w/10k down 1x cpu clock cpu t y pe 386/486 selection ccs3# 198 strap ccs3# hi g h for 486 interface w/10k down 386-t y pe interface resume reset selection * sa1 148 strap sa1 hi g h for rsmrst# on epmi2 w/10k , otherwise defaults to normal rst4# reset down no rsmrst# on epmi2** ca25/rdyi# selection sbhe# 161 strap sbhe# hi g h for pin 139 = ca25 , otherwise pin 89 defaults to rdyi# down pin 139 is rdyi# ** cpu interface level * nmi 120 strap nmi low w/10k for 5.0v cpu; otherwise , 3.3v cpu assumed up 3.3v cpu interface isa bus interface level * intr 121 strap intr low w/10k for 3.3v isa bus; otherwise , 5.0v isa bus assumed up 5.0v isa bus interface 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 7 revision: 3.0 3.3.1 mixed voltage interface options pins 120 and 121 provide strap options to select internal level translation of interface si g nals before the core lo g ic interface. pin 120 selects the cpu interface level , and pin 121 selects the isa bus interface level. with no straps , the option defaults to a 3.3v cpu and a 5.0v isa bus. the proper selections depend on the volta g e applied to each power plane; the vcc pins for each power plane are listed in the power and ground pins table of the pin descriptions section that follows. table 3-3 shows the proper strap settin g s for each volta g e mix. using 5v tolerant cpus it is hi g hl y recommended that the 5v-tolerant feature of cpus not be used with the opti 82c465 series chip. the 82c465 core should instead be powered at the 3.3v applied to the cpu interface. the reason for this recommendation it that the dma timin g on the 82c465 series is not met b y 5v-tolerant cpus. when the 82c465 chip cpu interface is runnin g at 5v , the translator from cpu 5v to 82c465 core 3.3v induces a deal y that ma y ne g ativel y impact dma timin g re q uirements. 3.3.2 resume reset (rsmrst#) function pin 148 strappin g works in con j unction with syscfg 40h [ 0 ] to determine whether pin 185 acts as a reset line that to gg les upon resumin g from suspend mode. refer to section 4.3.1.4 , "resume reset (rsmrst#) function" on pa g e 39 for com- plete information on this option. 3.3.3 reading the 1x/2x strap setting the state of the 1x/2x cpu strappin g selection can be read back throu g h syscfg 35h [ 3 ], as shown in table 3-4. table 3-3 strap settings for interface voltages notes: 1 ) pins 120 and 121 are never both strapped at the same time. 2 ) the combination of cpu interface at 5.0v and isa bus interface at 3.3v is not allowed , re g ardless of core volta g e. 3 ) if the core is operatin g at 3.3v , both the cpu and isa bus interfaces must be at 3.3v as well. table 3-4 1x/2x strapping readback register bit cpu interface voltage isa bus interface voltage core operating voltage pin 120 (nmi) pin 121 (intr) 3.3v 3.3v 3.3v no strap strap 3.3v 5.0v 3.3v no strap no strap 5.0v 5.0v 5.0v strap no strap 76543210 syscfg 35h dram control register 2 default = ffh ccs2# ( pin 3 ) strappin g ( ro ) : 0 = 2x cpu 1 = 1x cpu 82C465MV/mva/mvb opti ? pa g e 8 912-3000-016 revision: 3.0 3.3.4 using strap options with ttl logic as previousl y stated , the 82C465MV series chips incorporate strap option sensin g mechanisms that operate onl y at hard- ware reset time. this feature depends on chip si g nal pins that are normall y outputs: at reset time , the pins temporaril y become inputs so that the chip can sense whether the pins are bein g pulled hi g h or low b y the strap resistors. each of these strap option pins has a weak internal resistor so that no external resistor is needed for the most common selection options. this scheme was developed for use with cmos lo g ic devices , which draw ne g li g ible current at their inputs. how- ever , the 82C465MV series can also be used in applications in which ttl lo g ic is preferred. this situation creates a prob- lem for the strap option selections , because the internal resis- tors are no lon g er sufficient to brin g the inputs to 0v or to vcc because of the current draw of ttl parts. even stron g external resistors ma y not be sufficient if multiple ttl devices are connected to the same pin. therefore , when usin g ttl parts it is recommended that all strap pins connected to ttl be driven to their correct level at reset time. a 74244-t y pe buffer can be used. connect the "enable" pin of the buffer to rst4# of the chip. figure 3-1 rst4# and buffer connection pull-up t y pe strap option pull-up t y pe strap option pull-up t y pe strap option pull-up t y pe strap option do0 do1 do2 do3 di0 di1 di2 di3 vcc rst4# en 1/2 of 244 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 9 revision: 3.0 3.4 program selected interface options several interface options that are not critical to s y stem start- up are selectable throu g h confi g uration re g ister bits. some of these options can even be switched d y namicall y, if external lo g ic is in place to support such an arran g ement. 3.4.1 dackmux decoder lines source the s y stem desi g ner must determine whether there is a need for the dackmux interface , the interface that g enerates the dack#0-7 si g nals throu g h an external decoder. man y porta- ble s y stems use onl y dma channel 2 , which is available throu g h dedicated drq2/dack2# pins on the 82C465MV. however , if other dma channels must be provided , the dackmux si g nal interface must be recovered b y one of two means: ? deletin g the ma11 , mdir , and ras4# si g nals of the mem- or y interface. this option is described in the reduced memor y confi g uration si g nal group section. ? relocatin g the epmi1 , epmi2 , lowbat , and llowbat pins b y pro g rammin g syscfg a0h [ 3 ] = 1. table 3-5 indi- cates the reassi g nment that takes place. the hardware initialization bios code must select the dack- mux replacement interface pro g rammaticall y after reset b y settin g syscfg a0h [ 3 ] = 1. fi g ure 3-2 illustrates the t y pical connection. the optional 82c602a chip incorporates this decoder. table 3-5 program-selected dackmux interface recovery table 3-6 dackmux interface option enabling figure 3-2 standard dackmux0-2 connection (syscfg a0h[3] = 1) pin normal signal (syscfg a0h[3] = 0) optional dackmux replacement (syscfg a0h[3] = 1) 184 epmi1 dackmux2 185 epmi2 dackmux1 163 lowbat dackmux0 182 llowbat pmimux 76543210 syscfg a0h feature control register 1 default = 00h enable alterna- tive dackmux interface: 0 = disable 1 = enable see table 3-5 82C465MV 163 185 184 dackmux0 dackmux1 dackmux2 a b c 74138 dack0# dack1# dack2# dack3# dack5# dack6# dack7# n/c 82C465MV/mva/mvb opti ? pa g e 10 912-3000-016 revision: 3.0 3.4.2 epmi signal source if the dackmux pin functions have been moved to pins 184 , 185 , and 163 b y settin g syscfg a0h [ 3 ] = 1 , then the dis- placed si g nal set lowbat , llowbat , epmi1 , and epmi2 can be recovered throu g h an external multiplexer. this multi- plexer will scan each input for status chan g es at the rate of once ever y 280ns. the si g nals are sampled throu g h the mul- tiplexer as shown in table 3-7. one-half of an external 74153-t y pe multiplexer is re q uired to return the selected sam- ple throu g h pin 182 ( pmimux ) of the 82C465MV interface. see fi g ure 3-3 for a t y pical connection example. note that if j ust one of these power mana g ement input si g - nals will be needed , it is easiest to eliminate the multiplexer and connect the re q uired si g nal directl y to the pmimux input of the 82C465MV. the unneeded epmi inputs can simpl y be pro g rammed to be i g nored. table 3-7 pmimux multiplex option 3.4.2.1 additional epmi sources the 82C465MV can use one-half of a 74153 multiplexer to provide two new si g nals , epmi3 and epmi4. this feature is convenient if one-half of the 74153 multiplexer is alread y bein g used to brin g in lowbat , llowbat , epmi1 , and epmi2 as described above. when this feature is enabled b y settin g syscfg a1h [ 5 ] = 1 , pin 88 chan g es from the drq2 input to the epmmux input ( the output of the multiplexer ) . on the multiplexer itself , pins are defined as shown in table 3-2. fi g ure 3-3 illustrates how all epmi pins can be multiplexed in usin g a sin g le device when dackmux interface has dis- placed the epmi-2 , lowbat , and llowbat si g nals. table 3-8 epmmux multiplex option figure 3-3 multiplexed epmi input connections table 3-9 epmmux option enabling 74153 mux pin signal a ( input ) kbclk b ( input ) kbclk2 c0 ( input ) lowbat c1 ( input ) llowbat c2 ( input ) epmi1 c3 ( input ) epmi2 y ( output ) pmimux 74153 mux pin signal optional signal a ( input ) kbclk b ( input ) kbclk2 c0 ( input ) drq2 c1 ( input ) athold ( mva ) c2 ( input ) epmi3 ri# when syscfg fah [ 5 ] = 1 ( mvb ) c3 ( input ) epmi4 chck# when syscfg fah [ 4 ] = 1 ( mvb ) y ( output ) epmmux 82C465MV pmimux epmmux kbclk2 kbclk 182 88 167 158 7 9 1y 2y 74153 1c0 1c1 1c2 1c3 2c0 2c1 2c3 a b 1g 2g 6 5 4 3 10 11 12 13 14 2 1 15 lowbat llowbat epmi1 epmi2 drq2 epmi3/ri# epmi4/chck# 2c2 athold 76543210 syscfg a1h feature control register 2 default = 00h pin 88 - for epmi3-4: 0 = drq2 1 = epmmux 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 11 revision: 3.0 3.5 standard mode 82C465MV interface in its standard mode , the full complement of memor y control options are available on the 82C465MV chip. fi g ure 3-4 illus- trates the chip pinout in its standard mode , which re q uires strappin g pin 198 hi g h at reset. this fi g ure also assumes that the full dackmux0-2 interface is re q uired and is enabled throu g h settin g syscfg a0h [ 3 ] = 1. figure 3-4 pin diagram - standard mode 197 198 199 200 201 202 203 204 205 206 207 208 cd24 ccs3# cd23 vss vcc3 cd22 cd21 cd20 cd19 cd18 cd17 vss 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 vcc5 kbclk m16# lmegcs#/atcyc# sbhe# bale dackmux0 vss vcc5 oscclk kbclk2 rtcas rst4# aen pio3/stpgnt# pio2/atclkin pio1/nows# pio0/lreq# tc dbe# spkd io16# chck# osc14 sqwin pmimux susp/rsm# dackmux2 dackmux1 master#/ri# rst1# ppwrl lclk cd31 cd30 cd29 cd28 cd27 cd26 cd25 117 116 115 114 113 112 111 110 109 108 107 106 105 rdy# hold vcc3 brdy# blast# ads# sd0 sd1 sd2 sd3 sd4 vss 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 atclk mrd# mwr# iord# iowr# chrdy# xdir sa1 vcc5 sa0 rfsh# fbclkin fbclkout vss cpuclk ldev# ca25/rdyi# ignne# smi# smiact# flush# eads# m/io# w/r# d/c# a20m# ferr# holda be3# be2# be1# be0# ahold sreset intr nmi vss stpclk# ken# ca12 ca13 ca14 ca15 vcc5 vss ca16 ca17 ca18 ca19 ca20 ca21 kbdcs# sd5 sd6 sd7 sd8 sd9 sd10 vcc5 vss sd11 sd12 sd13 sd14 sd15 romcs# rtcd# epmmux irq5 irq9 irq11 rqmx0 rqmx1 rqmx2 rqmx3 lgnt# mdir ras4# ma11 ca2 ca3 ca4 ca5 ca6 vss ca7 ca8 ca9 ca10 ca11 vss vcc3 64 63 62 61 60 59 58 57 56 55 54 53 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ma4 ma3 vcc3 ma2 ca31 ca24 ca23 ca22 ma1 ma0 cas0# vss vcc3 cd16 ccs2# cd15 cd14 cd13 cd12 cd11 cd10 vcc5 cd9 cd8 ccs1# cd7 vss cd6 cd5 cd4 cd3 cd2 cd1 cd0 ccs0# ras3# dwe# vss cas3# ras2# ras1# ras0# ma9 ma10 cpurst ma8 ma7 ma6 cas2# vss cas1# ma5 82C465MV/mva/mvb 82C465MV/mva/mvb opti ? pa g e 12 912-3000-016 revision: 3.0 3.5.1 reduced memory interface signal group option the standard 82C465MV dram controller hardware includes direct control of up to five banks of dram ( ras0#-ras4# ) and up to 12 bits of s y mmetrical or as y mmetrical dram addressin g ( ma [ 11:0 ]), and provides memor y data buffer direction control ( mdir ) . to maintain backward compatibilit y with 82c463mv-based applications , three si g nals must be redefined: ma11 , mdir , and ras4#. the three memor y si g nals are disabled b y a strap option: if pin 79 is pulled hi g h at reset time , the chipset initialization lo g ic will redefine three pins with their corre- spondin g 82c463mv-located si g nals of dackmux0 , 1 , and 2. the memor y features will not be available. table 3-10 lists the pin chan g es. if pin 79 is left floatin g at reset , a weak internal pull-down resistor straps the line low and the 82C465MV memor y inter- face si g nals will be available. if pin 79 is pulled hi g h at reset , the old 82c463mv-compatible dackmux interface will be in effect. all 82c463mv desi g ns re q uired pin 79 to be pulled hi g h at reset; conse q uentl y, replacin g an 82c463mv chip with the 82C465MV part automaticall y establishes the proper interface scheme for backward compatibilit y . note: when the dackmux0-2 si g nals are used from pins 77-79 , the y are provided on the cpu interface power plane. therefore , in a mixed-volta g e s y stem , these will be 3.3v si g nals. the appropriate lo g ic famil y must be considered when selectin g the dack decoder to avoid the hi g h current associated with drivin g 3.3v si g nals to 5.0v-powered lo g ic. fi g ure 3-5 illustrates the 82C465MV pinout in its 82c463mv- compatible mode , selected b y strappin g pins 79 and 198 hi g h at reset. table 3-10 strap-selected reduced memory interface option pin normal 82C465MV (pin 79 low at reset) reduced memory interface (pin 79 high at reset) 77 ma11 dackmux2 78 ras4# dackmux1 79 mdir dackmux0 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 13 revision: 3.0 figure 3-5 pin diagram - 82c463mv-compatible mode 197 198 199 200 201 202 203 204 205 206 207 208 cd24 ccs3# cd23 vss vcc3 cd22 cd21 cd20 cd19 cd18 cd17 vss 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 vcc5 kbclk m16# lmegcs#/atcyc# sbhe# bale lowbat vss vcc5 oscclk kbclk2 rtcas rst4# aen pio3/stpgnt# pio2/cpuspd pio1/nows# pio0 tc tris# spkd io16# chck# osc14 sqwin llowbat susp/rsm# epmi1 epmi2 master#/ri# rst1# ppwrl lclk cd31 cd30 cd29 cd28 cd27 cd26 cd25 117 116 115 114 113 112 111 110 109 108 107 106 105 rdy# hold vcc3 brdy# blast# ads# sd0 sd1 sd2 sd3 sd4 vss 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 atclk mrd# mwr# iord# iowr# chrdy# xdir sa1 vcc5 sa0 rfsh# fbclkin fbclkout vss cpuclk ldev# ca25/rdyi# ignne# smi# smisct# flush# eads# m/io# w/r# d/c# a20m# ferr# holda be3# be2# be1# be0# ahold sreset intr nmi vss stpclk# ken# ca12 ca13 ca14 ca15 vcc5 vss ca16 ca17 ca18 ca19 ca20 ca21 kbdcs# sd5 sd6 sd7 sd8 sd9 sd10 vcc5 vss sd11 sd12 sd13 sd14 sd15 romcs# rtcd# dreq2 irq5 irq9 irq11 rqmx0 rqmx1 rqmx2 rqmx3 dack2# dackmux0 dackmux1 dackmux2 ca2 ca3 ca4 ca5 ca6 vss ca7 ca8 ca9 ca10 ca11 vss vcc3 64 63 62 61 60 59 58 57 56 55 54 53 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ma4 ma3 vcc3 ma2 ca31 ca24 ca23 ca22 ma1 ma0 cas0# vss vcc3 cd16 ccs2# cd15 cd14 cd13 cd12 cd11 cd10 vcc5 cd9 cd8 ccs1# cd7 vss cd6 cd5 cd4 cd3 cd2 cd1 cd0 ccs0# ras3# dwe# vss cas3# ras2# ras1# ras0# ma9 ma10 cpurst ma8 ma7 ma6 cas2# vss cas1# ma5 82c463mv-compatible mode 82C465MV/mva/mvb opti ? pa g e 14 912-3000-016 revision: 3.0 3.5.2 82C465MV interface with l2 cache support an optional mode for the 82C465MV chipset provides a com- plete , direct set of cache control si g nals to an external write- back cache. this option is enabled b y strappin g pin 146 low and pin 198 hi g h at reset. the external pin interface chan g es substantiall y with this option. fi g ure 3-6 illustrates the pinout in this mode. figure 3-6 pin diagram - 82C465MV interface with l2 cache support 197 198 199 200 201 202 203 204 205 206 207 208 drty ccs3# tag7 vss vcc3 tag6 tag5 tag4 tag3 tag2 tag1 vss 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 vcc5 kbclk m16# lmegcs#/atcyc# sbhe# bale dackmux0 vss vcc5 oscclk kbclk2 rtcas rst4# aen pio3/stpgnt# pio2/atclkin pio1/nows# pio0/lreq# tc dbe# spkd io16# chck# osc14 sqwin pmimux susp/rsm# dackmux2 dackmux1 master#/ri# rst1# ppwrl tagcs# eca3 eca2 tagwe# ocawe# ecawe# booe# beoe# 117 116 115 114 113 112 111 110 109 108 107 106 105 rdy# hold vcc3 brdy# blast# ads# sd0 sd1 sd2 sd3 sd4 vss 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 atclk mrd# mwr# iord# iowr# chrdy# sdir sa1 vcc5 sa0 rfsh# fbclkin fbclkout vss cpuclk ldev# ca25/rdyi# ignne# smi# smisct# flush# eads# m/io# w/r# d/c#/hitm# a20m# ferr# holda be3# be2# be1# be0# ahold sreset intr nmi vss stpclk# ken# ca12 ca13 ca14 ca15 vcc5 vss ca16 ca17 ca18 ca19 ca20 ca21 sdenh# sd5 sd6 sd7 sd8 sd9 sd10 vcc5 vss sd11 sd12 sd13 sd14 sd15 romcs#/rtcd# sdenl# epmmux irq5 irq9 irq11 rqmx0 rqmx1 rqmx2 rqmx3 lgnt# mdir ras4# ma11 ca2 ca3 ca4 ca5 ca6 vss ca7 ca8 ca9 ca10 ca11 vss vcc3 64 63 62 61 60 59 58 57 56 55 54 53 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ma4 ma3 vcc3 ma2 ca31 ca24 ca23 ca22 ma1 ma0 cas0# vss vcc3 tag0 ccs2# cd15 cd14 cd13 cd12 cd11 cd10 vcc5 cd9 cd8 ccs1# cd7 vss cd6 cd5 cd4 cd3 cd2 cd1 cd0 ccs0# ras3# dwe#kbdcs# vss cas3# ras2# ras1# ras0# ma9 ma10 cpurst ma8 ma7 ma6 cas2# vss cas1# ma5 82C465MV interface with l2 cache support 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 15 revision: 3.0 3.5.3 82C465MV with 386 interface the 82C465MV chipset offers the option of a 386dx-t y pe interface. this confi g uration supports processors like the ibm blue li g htnin g . it is enabled b y default with no strap pins. fi g - ure 3-7 illustrates the 386 interface mode. figure 3-7 pin diagram - 386 interface mode 197 198 199 200 201 202 203 204 205 206 207 208 cd24 ccs3# cd23 vss vcc3 cd22 cd21 cd20 cd19 cd18 cd17 vss 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 vcc5 kbclk m16# lmegcs#/atcyc# sbhe# bale dackmux0 vss vcc5 oscclk kbclk2 rtcas rst4# aen dfsrdy# pio2/atclkin pio1/nows# lreq# tc dbe# spkd io16# chck# osc14 sqwin pmimux susp/rsm# dackmux2 dackmux1 master#/ri# rst1# ppwrl lclk cd31 cd30 cd29 cd28 cd27 cd26 cd25 117 116 115 114 113 112 111 110 109 108 107 106 105 rdy# hold vcc3 error# npbsy# ads# sd0 sd1 sd2 sd3 sd4 vss 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 atclk mrd# mwr# iord# iowr# chrdy# sdir sa1 vcc5 sa0 rfsh# fbclkin fbclkout vss cpuclk ldev# ca25/rdyi# busy# pwi# pwiads# nprst# eads# m/io# w/r# d/c# a20m# ferr# holda be3# be2# be1# be0# ahold 0vcpurst intr nmi vss dfsreq# ken# ca12 ca13 ca14 ca15 vcc5 vss ca16 ca17 ca18 ca19 ca20 ca21 kbdcs# sd5 sd6 sd7 sd8 sd9 sd10 vcc5 vss sd11 sd12 sd13 sd14 sd15 romcs# rtcd# epmmux/dreq2 irq5 irq9 irq11 rqmx0 rqmx1 rqmx2 rqmx3 lgnt# mdir ras4# ma11 ca2 ca3 ca4 ca5 ca6 vss ca7 ca8 ca9 ca10 ca11 vss vcc3 64 63 62 61 60 59 58 57 56 55 54 53 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ma4 ma3 vcc3 ma2 ca31 ca24 ca23 ca22 ma1 ma0 cas0# vss vcc3 cd16 ccs2# cd15 cd14 cd13 cd12 cd11 cd10 vcc5 cd9 cd8 ccs1# cd7 vss cd6 cd5 cd4 cd3 cd2 cd1 cd0 ccs0# ras3# dwe# vss cas3# ras2# ras1# ras0# ma9 ma10 vlbusrst ma8 ma7 ma6 cas2# vss cas1# ma5 82C465MV 386 interface mode 82C465MV/mva/mvb opti ? pa g e 16 912-3000-016 revision: 3.0 3.6 pin signal characteristics the si g nal t y pes , drive capabilities , si g nal directions , power plane , and other information for each pin on the 82C465MV is provided in table 3-11. the followin g le g end applies to the table entries. legend note that internal pull-up and pull-down resistors are en g a g ed onl y durin g bus hold condition ( which includes sus- pend mode ), or onl y at hardware reset time ( rst1# active ) if so indicated. external pull-up resistors are su gg ested but ma y not be desirable in all cases ( zero-volt suspend cpus , for example ) . table 3-11 82C465MV pin characteristics d driven ( to the last state before suspend ) dh driven hi g h dl driven low drive ( ma ) maximum recommended stead y state out- put current for each pin , assumin g rated current loadin g on all pins at once. ext external i ttl-level input ic cmos-level input int internal is schmitt-tri gg er-level input o cmos-level output od open-drain ( open-collector ) cmos output pd pull-down pu pull-up ts tristated pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 1 cpuvcc -- cpu 2 cd16/tag0 i/o ( 4ma ) int pd ts cpu 3 ccs2# i/o ( 4ma ) int pd on reset ts or dh 1 cpu 4 cd15 i/o ( 4ma ) int pd ts cpu 5 cd14 i/o ( 4ma ) int pd ts cpu 6 cd13 i/o ( 4ma ) int pd ts cpu 7 cd12 i/o ( 4ma ) int pd ts cpu 8 cd11 i/o ( 4ma ) int pd ts cpu 9 cd10 i/o ( 4ma ) int pd ts cpu 10 corevcc -- core 11 cd9 i/o ( 4ma ) int pd ts cpu 12 cd8 i/o ( 4ma ) int pd ts cpu 13 ccs1# i/o ( 4ma ) int pd on reset ts or dh 1 cpu 14 cd7 i/o ( 4ma ) int pd ts cpu 15 gnd -- gnd 16 cd6 i/o ( 4ma ) int pd ts cpu 17 cd5 i/o ( 4ma ) int pd ts cpu 18 cd4 i/o ( 4ma ) int pd ts cpu 19 cd3 i/o ( 4ma ) int pd ts cpu 20 cd2 i/o ( 4ma ) int pd ts cpu 21 cd1 i/o ( 4ma ) int pd ts cpu 22 cd0 i/o ( 4ma ) int pd ts cpu 23 ccs0# i/o ( 4ma ) int pd on reset ts or dh 1 cpu 24 ras3# o ( 8/12ma ) dcpu 25 dwe# ( +kbdcs# ) o ( 8/12ma ) dh cpu 26 gnd -- gnd 27 cas3# o ( 8ma ) dcpu 28 ras2# o ( 8/12ma ) dcpu 29 ras1# o ( 8/12ma ) dcpu 30 ras0# o ( 8/12ma ) dcpu 31 ma9 o ( 8/12ma ) dcpu 32 ma10 o ( 8/12ma ) dcpu 33 cpurst o ( 8ma ) dl cpu pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 17 revision: 3.0 34 ma8 o ( 8/12ma ) dcpu 35 ma7 o ( 8/12ma ) dcpu 36 ma6 o ( 8/12ma ) dcpu 37 cas2# o ( 8ma ) dcpu 38 gnd -- gnd 39 cas1# o ( 8ma ) dcpu 40 ma5 o ( 8/12ma ) dcpu 41 ma4 o ( 8/12ma ) dcpu 42 ma3 o ( 8/12ma ) dcpu 43 cpuvcc -- cpu 44 ma2 o ( 8/12ma ) dcpu 45 ca31 i int pd ts cpu 46 ca24 i int pd ts cpu 47 ca23 i/o ( 4ma ) int pd ts cpu 48 ca22 i/o ( 4ma ) int pd ts cpu 49 ma1 o ( 8/12ma ) dcpu 50 ma0 o ( 8/12ma ) dcpu 51 cas0# o ( 8ma ) dcpu 52 gnd -- gnd 53 cpuvcc -- cpu 54 ca21 i/o ( 4ma ) int pd ts cpu 55 ca20 i/o ( 4ma ) int pd ts cpu 56 ca19 i/o ( 4ma ) int pd ts cpu 57 ca18 i/o ( 4ma ) int pd ts cpu 58 ca17 i/o ( 4ma ) int pd ts cpu 59 ca16 i/o ( 4ma ) int pd ts cpu 60 gnd -- gnd 61 corevcc -- core pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 62 ca15 i/o ( 4ma ) int pd ts cpu 63 ca14 i/o ( 4ma ) int pd ts cpu 64 ca13 i/o ( 4ma ) int pd ts cpu 65 ca12 i/o ( 4ma ) int pd ts cpu 66 ca11 i/o ( 4ma ) int pd ts cpu 67 ca10 i/o ( 4ma ) int pd ts cpu 68 ca9 i/o ( 4ma ) int pd ts cpu 69 ca8 i/o ( 4ma ) int pd ts cpu 70 ca7 i/o ( 4ma ) int pd ts cpu 71 gnd -- gnd 72 ca6 i/o ( 4ma ) int pd ts cpu 73 ca5 i/o ( 4ma ) int pd ts cpu 74 ca4 i/o ( 4ma ) int pd ts cpu 75 ca3 i/o ( 4ma ) int pd ts cpu 76 ca2 i/o ( 4ma ) int pd ts cpu 77 ma11/ dackmux2 o ( 8ma ) int pd on reset d/ts cpu 78 ras4#/ dackmux1/ cdir o ( 8ma ) int pu on reset d/ts cpu 79 mdir/ dackmux0 o ( 4ma ) int pd on reset dh/ts cpu 80 dack2#/lgnt# o ( 4ma ) ext 20k w pu ts cpu 81 rqmx3 is atio 82 rqmx2 is atio 83 rqmx1 is atio 84 rqmx0 is atio 85 irq11 i atio 86 irq9 i atio 87 irq5 i atio 88 dreq2/ epmmux is atio 89 rtcd#/ sdenl# o ( 4ma ) rtcd#: ext 20k w pu ts/dh atio pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane table 3-11 82C465MV pin characteristics (cont.) 82C465MV/mva/mvb opti ? pa g e 18 912-3000-016 revision: 3.0 90 romcs# ( /+rtcd# ) o ( 4ma ) ext 20k w pu ts atio 91 sd15 i/o ( 8ma ) ext 10k w pu ts atio 92 sd14 i/o ( 8ma ) ext 10k w pu ts atio 93 sd13 i/o ( 8ma ) ext 10k w pu ts atio 94 sd12 i/o ( 8ma ) ext 10k w pu ts atio 95 sd11 i/o ( 8ma ) ext 10k w pu ts atio 96 gnd -- gnd 97 atiovcc -- atio 98 sd10 i/o ( 8ma ) ext 10k w pu ts atio 99 sd9 i/o ( 8ma ) ext 10k w pu ts atio 100 sd8 i/o ( 8ma ) ext 10k w pu ts atio 101 sd7 i/o ( 8ma ) ext 10k w pu ts atio 102 sd6 i/o ( 8ma ) ext 10k w pu ts atio 103 sd5 i/o ( 8ma ) ext 10k w pu ts atio 104 kbdcs#/ sdenh# o ( 4ma ) kbdcs#: ext 20k w pu ts/dh atio 105 gnd -- gnd 106 sd4 i/o ( 8ma ) ext 10k w pu ts atio 107 sd3 i/o ( 8ma ) ext 10k w pu ts atio 108 sd2 i/o ( 8ma ) ext 10k w pu ts atio 109 sd1 i/o ( 8ma ) ext 10k w pu ts atio 110 sd0 i/o ( 8ma ) ext 10k w pu ts atio 111 ads# i/o ( 4ma ) ext 10k w pu ts cpu 112 blast#/ npbusy# i ext 10k w pu cpu 113 brdy#/ error# i/o ( 4ma ) int cpu pu ts cpu 114 cpuvcc cpu 115 hold o ( 4ma ) d2cpu pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 116 rdy# i/o ( 4ma ) ext 10k w pu ts cpu 117 ken# o ( 4ma ) int cpu pu ts cpu 118 stpclk# o ( 4ma ) int cpu pu dl 4 cpu 119 gnd -- gnd 120 nmi i/o ( 4ma ) int pu on reset dl cpu 121 intr i/o ( 4ma ) int pu on reset dl cpu 122 sreset o ( 8ma ) dl cpu 123 ahold o ( 4ma ) dl cpu 124 be0# i/o ( 4ma ) int pd ts cpu 125 be1# i/o ( 4ma ) int pd ts cpu 126 be2# i/o ( 4ma ) int pd ts cpu 127 be3# i/o ( 4ma ) int pd ts cpu 128 hlda i cpu 129 ferr# i int pu cpu 130 a20m#/ga20 i/o ( 4ma ) int cpu pu ts cpu 131 dc#+hitm# i int pd 5 cpu 132 w/r# i/o ( 4ma ) int pd cpu 133 m/io# i/o ( 4ma ) int pd cpu 134 eads# /nprst# o ( 4ma ) int cpu pu ts cpu 135 flush#/ smirdy#/ hitm# i/o ( 4ma ) int cpu pu ts cpu 136 smiact#/ smiads# icpu 137 smi# i/o ( 4ma ) int cpu pu ts cpu 138 ignne#/busy# o ( 4ma ) int cpu pu ts cpu 139 ca25/rdyi# i int pd cpu 140 ldev# i cpu 141 cpuclk o ( 8ma ) dl cpu 142 gnd gnd pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane table 3-11 82C465MV pin characteristics (cont.) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 19 revision: 3.0 143 fbclkout o ( 8ma ) cpu 144 fbclkin ic cpu 145 rfsh# i/o ( 8ma ) ts atio 146 sa0 i/o ( 8ma ) int pu on reset ts atio 147 vdds atio 148 sa1 i/o ( 8ma ) int pd on reset ts atio 149 xdir/sdir o ( 4ma ) dh atio 150 chrdy is/od ( 8ma ) ts atio 151 iowr# i/o ( 8ma ) ts atio 152 iord# i/o ( 8ma ) ts atio 153 mwr# i/o ( 8ma ) ts atio 154 mrd# i/o ( 8ma ) ts atio 155 atclk o ( 8ma ) dl atio 156 gnd gnd 157 corevcc core 158 kbclk o ( 4ma ) runs atio 159 m16# is/o ( 8ma ) ts atio 160 lmegcs#+ atcyc# o ( 4ma ) int pd on reset ts atio 161 sbhe#/dwr# i/o ( 8ma ) int pd on reset ts atio 162 bale o ( 8ma ) dl atio 163 lowbat/ dackmux0 i/o ( 4ma ) int pd dis- abled on suspend and when pin is out- put ts atio 164 gnd gnd gnd 165 atiovcc atio 166 oscclk ic atio 167 kbclk2 o ( 4ma ) runs atio 168 rtcas o ( 4ma ) dl atio pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 169 rst4# o ( 4ma ) atio 170 aen o ( 8ma ) dl atio 171 pio3/ stpgnt# i/o ( 4ma ) atio 172 pio2/cpuspd/ atclkin/ sabufen# i/o ( 4ma ) atio 173 pio1/nows#/ cmd# i/o ( 4ma ) atio 174 pio0/lreq# i/o ( 4ma ) atio 175 tc/drd# o ( 4ma ) dl atio 176 tris#/dbe# o ( 4ma ) int pu on reset atio 177 spkd o ( 4ma ) ts atio 178 io16# is atio 179 chck#/ kbcrstin is atio 180 osc14 i atio 181 sqwin i atio 182 llowbat/ pmimux iatio 183 susp/rsm i atio 184 epmi1/ dackmux2 i/o ( 4ma ) int pu dis- abled on suspend and when pin is out- put ts atio 185 epmi2/ dackmux1 i/o ( 4ma ) int pd dis- abled on suspend and when pin is out- put ts 3 atio 186 master#/ ri/sel#-atb# iatio 187 rst1# is atio 188 ppwrl o ( 4ma ) dl cpu 189 lclk/tagcs#/ boff# o ( 4ma ) ts or dh 1 cpu 190 cd31/eca3 i/o ( 8ma ) int pd ts cpu 191 cd30/eca2 i/o ( 8ma ) int pd ts cpu pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane table 3-11 82C465MV pin characteristics (cont.) 82C465MV/mva/mvb opti ? pa g e 20 912-3000-016 revision: 3.0 notes: 1. these pins can be driven hi g h durin g suspend if l2 cache is still powered , or can be tristated if cache is powered off , as selected throu g h syscfg d0h [ 6 ] . 2. these pins are driven low when zero-volt cpu suspend is selected throu g h syscfg adh [ 5 ] . 3. the epmi2 pin is driven durin g suspend if the chip is strapped for the rsmrst# option. 4. the cpu disconnects its stpgnt# pull-up dur- in g stop g rant c y cles. 5. d/c# still re q uires an external pull-up on the cpu side when the d/c#+hitm# g ate is used for l2 cache. 6. pins with dual drive capabilit y are set throu g h pro g ram re g isters. 192 cd29/tagwe# i/o ( 4ma ) int pd ts or dh 1 cpu 193 cd28/ocawe# i/o ( 8ma ) int pd ts or dh 1 cpu 194 cd27/ecawe# i/o ( 8ma ) int pd ts or dh 1 cpu 195 cd26/booe# i/o ( 8ma ) int pd ts or dh 1 cpu 196 cd25/beoe# i/o ( 8ma ) int pd ts or dh 1 cpu 197 cd24/drty i/o ( 4ma ) int pd ts cpu 198 ccs3# i/o ( 4ma ) int pd on reset ts or dh 1 cpu 199 cd23/tag7 i/o ( 4ma ) int pd ts cpu 200 gnd gnd 201 cpuvcc cpu 202 cd22/tag6 i/o ( 4ma ) int pd ts cpu 203 cd21/tag5 i/o ( 4ma ) int pd ts cpu 204 cd20/tag4 i/o ( 4ma ) int pd ts cpu 205 cd19/tag3 i/o ( 4ma ) int pd ts cpu pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane 206 cd18/tag2 i/o ( 4ma ) int pd ts cpu 207 cd17/tag1 i/o ( 4ma ) int pd ts cpu 208 gnd gnd pin no. signal name pin type (drive) pu/pd, where bus hold/ suspend level note pwr plane table 3-11 82C465MV pin characteristics (cont.) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 21 revision: 3.0 3.7 signal descriptions references throu g hout the pin descriptions depend on the chip strappin g options made , as described in section 3.3 , "strap-selected interface options" on pa g e 5. refer to table 3-2 to determine the features that are mutuall y exclusive. internal pull-ups or pull-downs are not listed here , but can be found in table 3-11 on pa g e 16. 3.7.1 clock and reset interface signal name pin no signal type selected by signal description oscclk 166 i-cmos oscillator clock input: fixed at the on-mode fre q uenc y of the cpu. atcyc# strappin g option also allows it to be 2x for a 1x cpu clock if desired. fbclkin 144 i-cmos feedback clock input: this si g nal is used to clock most of the internal circuitr y . this input should be connected to fbclkout. fbclkout 143 o system feedback clock output: this si g nal should be connected to the 82C465MV fbclkin input throu g h a discrete passive component ( 33 w resistor is t y pical ) . this output is 1x , re g ardless of whether a 1x or 2x cpu is bein g used. cpuclk 141 o cpu clock output: this output is 1x for 1x clock cpus and 2x for 2x clock cpus. it should be connected to the cpu clock input throu g h a discrete passive component ( 33 w resistor is t y pical ) . sqwin 181 i square wave input: this clock input ma y be 32khz or 128khz. this clock input is used to clock the internal power mana g ement timers. this clock is also used to time refresh fre q uenc y, both active and durin g suspend ( if suspend refresh is pro g rammed ) . set syscfg 40h [ 3 ] to indicate the input fre q uenc y used. osc14 180 i 14.318mhz clock input: this si g nal g oes to the ipc timer , times refresh pulse width except durin g suspend mode , and can be enabled to time isa bus operations. this input can be turned off durin g suspend mode if the kbclk source is set to 32khz ( syscfg 66h [ 6 ]) or if no kbclk and interrupt scannin g is needed. kbclk 158 o keyboard controller clock: also used with kbclk2 to multiplex irqs , drqs , and epmi inputs. kbclk2 167 o keyboard controller clock divided by two: also used with kbclk to multiplex interrupts and dma re q uests. rst1# 187 is reset one: initiates a cold reset from the power suppl y or reset switch. rst4# 169 o reset four: indicates a cold reset to the s y stem. cpurst 33 o cpu reset: standard cpu reset ( includes smbase reset for smi cpus ) . sreset 122 o cpu soft reset: partiall y resets the cpu ( the smbase is not reset for smi cpus ) . used as the main cpu reset for ibm blue li g htnin g . 82C465MV/mva/mvb opti ? pa g e 22 912-3000-016 revision: 3.0 3.7.2 cpu / vl-bus interface signal name pin no signal type selected by signal description cd [ 31:16 ] 190-197 , 199 , 202-7 i/o pin 146 strap option ( see table 3-2 ) upper cpu data bus word (no l2 cache mode) cache si g nals i/o cache data and control signals (l2 cache mode): see section 4.5.4 , "l2 cache support" on pa g e 64. cd [ 15:0 ] 2 , 4-9 , 11 , 12 , 14 , 16-22 i/o lower cpu data bus word ads# 111 i/o address strobe: as an input , this pin from the cpu indi- cates the start of a valid address c y cle. as an output , this si g nal is used to support the vesa local bus durin g isa bus access of local memor y ( isa masters and dma ) . m/io# 133 i/o memory or i/o: as an input , this si g nal from the cpu indi- cates whether the current c y cle is a memor y or i/o access. as an output , this si g nal is used to support the vesa local bus durin g isa bus access of local memor y ( isa masters and dma ) . w/r# 132 i/o write or read: this si g nal from the cpu indicates whether the current c y cle is a write or read access durin g isa bus access of local memor y ( isa masters and dma ) . d/c# 131 i c y cle multiplexed data or command: this si g nal from the cpu indicates whether the current c y cle is a data or code access. hitm# hit on modified line: cpu indication that the external master bus snoop initiated when eads# went active has hit upon a modified internal cache line , re q uirin g the cpu to update external dram before the master can continue. ca31 , ca24 45 , 46 i cpu address a31, a24 inputs: use stron g ( 2kohm ) pull- down on these lines as well as cpu ca [ 30:25 ] for proper dma operation. ca [ 23:10 ] 47 , 48 , 54-59 , 62-67 i/o cpu address lines a23 to a10: these pins are inputs for cpu and master c y cles. these pins are outputs for dma c y cles. ca [ 9:2 ] 68-70 , 72-76 i/o cpu address lines a9 to a2: these pins are inputs for cpu and master c y cles. these pins are outputs for dma and refresh c y cles. be [ 3:0 ] # 127-124 i/o byte enables: for cpu c y cles , these inputs are the cpu b y te enables. for isa bus access of local memor y, the y are outputs. rdy# 116 i/o ready: indicates completion of the current vl-bus c y cle. local bus devices can drive rdy# directl y to the cpu as lon g as the y use a tristate driver that does not drive while ldev# is inactive. hold 115 o hold request: re q uests s y stem control from the cpu. hlda 128 i hold acknowledge: cpu acknowled g es a hold re q uest with this si g nal. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 23 revision: 3.0 nmi 120 strap option pin , refer to table 3-2 o non maskable interrupt: indicates the occurrence of a non maskable interrupt to the cpu. intr 121 strap option pin , refer to table 3-2 o interrupt: indicates occurrence of a maskable interrupt to the cpu. ken# 117 o cache enable: indicates to the cpu that current bus c y cle is cacheable. brdy# 113 i/o pin 198 strap option ( see table 3-2 ) burst ready (486 mode): indicates termination of a burst c y cle. the 82C465MV controller lo g ic also terminates non burst c y cles with brdy# on occasion. error# i/o numeric processor error (386 mode): indicates a calcu- lation error from the numeric processor. eads# 134 o pin 198 strap option ( see table 3-2 ) external address strobe (486 mode): indicates that an external bus master has placed a valid address on the cpu address bus , and is used b y the cpu to invalidate internal cache ( and g enerate hitm# if available ) . nprst# o numerical processor reset (386 mode): this si g nal is used to reset the numeric coprocessor. ahold 123 o address hold request: the cpu will float its address bus in the clock followin g ahold g oin g active. the 82C465MV g enerates ahold after a cache writeback has been completed; ahold active while hitm# is inactive constitutes the boff# si g nal to the cpu. blast# 112 i pin 198 strap option ( see table 3-2 ) burst last (486 mode): indicates that the next brdy# will complete the current burst c y cle. npbusy# i numeric processor busy (386 mode): indication from the numeric processor that the current operation has not completed. ldev# 140 i local device: local devices drive this input to indicate that the y are respondin g to the current c y cle. this si g nal must be asserted b y the end of the first t2 ( with appropri- ate setup time ) for local device reco g nition. this si g nal has an internal 50k pull-up resistor. ca25 ( 64mb ) 139 i pin 161 strap option ( see table 3-2 ) ca25: address for increased local dram capacit y . this pin must function as ca25 if dram memor y size over 32mb is re q uired. rdyi# ( 32mb ) i rdyi# (lrdy# from vl-bus): local devices drive this input to indicate that the current c y cle is completed. the function of pin 139 is determined b y pin 161 strappin g . if ca25 is re q uired as well as lrdy# , the vl-bus device can drive the cpu rdy# si g nal directl y ( lrdy# is defined as open-collector ) up to 33mhz. signal name pin no signal type selected by signal description 82C465MV/mva/mvb opti ? pa g e 24 912-3000-016 revision: 3.0 ferr# 129 i floating point error: driven b y the coprocessor to indi- cate an error condition when an unmasked exception occurs. ignne# 138 o pin 198 strap option ( see table 3-2 ) ignore numeric errors (486 mode): instructs the cpu to i g nore the numeric coprocessor's error output. busy# o numeric processor busy (386 mode): indicates that the numeric co-processor has not completed its current opera- tion.` tagcs# 189 o pin 146 strap option ( see table 3-2 ) tag chip select (l2 cache mode): see section 4.5.4 , "l2 cache support" on pa g e 64. boff# o pin 146 strap option ( see table 3-2 ) and syscfg d4h [ 0 ] = 0 cpu backoff (no l2 cache mode): this pin becomes boff# to the cpu when there is no l2 cache present and the 465 memor y interface is enabled. lclk o pin 146 strap option ( see table 3-2 ) and syscfg d4h [ 0 ] = 1 local bus clock (pin 79 strapped high - 82c463mv- compatible mode only): for 2x clock cpus , this si g nal is the vesa local bus 1x clock. for 1x clock cpus , this si g - nal is a 2x clock output. ( in this mode , the vesa local bus 1x clock comes from pin 143 , fbclkout ) stpclk# 118 o stop clock: re q uests a chan g e in the clock fre q uenc y from the cpu. smi# 137 i/o system management interrupt: re q uest s y stem man- a g ement mode ( smm ) operation from the cpu. for sup- port of some cpus , this pin is bidirectional. see syscfg 5bh [ 4 ] . smiact# 136 i syscfg [ 5bh [ 4 ] = 0 smi process active or smi address strobe: this pin is used to indicate that the cpu is operatin g is s y stem man- a g ement mode ( smm ) . smiads# syscfg [ 5bh [ 4 ] = 1 flush# 135 o syscfg [ 6bh [ 6 ] = 0 cache flush: the flush# si g nal commands flushin g of the internal cpu cache on entr y to smm. smirdy# o syscfg [ 6bh [ 6 ] = 1 smi ready: the smirdy# si g nal responds to smiads# for cpus that re q uire this si g nal interface. hitm# i syscfg [ d6h [ 4 ] = 1 hit on modified line: cpu indication that the external master bus snoop initiated when eads# went active has hit upon a modified internal cache line , re q uirin g the cpu to update external dram before the master can continue. signal name pin no signal type selected by signal description 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 25 revision: 3.0 3.7.3 dram interface signal name pin no. signal type selected by description ccs [ 3:0 ] # 198 , 3 , 13 , 23 strap option pins , refer to table 3-2 o cache chip select 0-3 (l2 cache mode): these pins are strap options onl y, in the case where no l2 cache is used. dwe# 25 o pin 146 strap option ( see table 3-2 ) dram write enable (no l2 cache mode): for dram memor y c y cles , this si g nal is the dram write strobe. dwe#+ kbdcs# o dwe# combined with kbdcs# (l2 cache mode): this si g nal must be q ualified with aen low to decode the true kbdcs# si g nal. refer to the separate kbdcs# descrip- tion also. cas [ 3:0 ] #27 , 37 , 39 , 51 o column address strobes 3 to 0: these outputs drive the cas# inputs on dram b y tes 3 to 0. ras [ 3:0 ] #24 , 28 , 29 , 30 o row address strobes 3 to 0: these outputs drive the ras# inputs on dram banks 3 to 0. ras4# 78 o syscfg f8h [ 1 ] = 0 and pin 79 strap option not used row address strobe 4: this output drives the ras# input from dram bank 4. note that ras4# is not available if pin 79 strappin g option is used to defeat it. cdir o syscfg f8h [ 1 ] = 1 compact isa direction: controls buffer direction for cisa cable drive buffer. mdir 79 strap option pin , refer to table 3-2 o memory buffer direction signal: note that this si g nal is not available if pin 79 strappin g option is used to defeat it. ma11 77 o memory address signal ma11: note that this si g nal is not available if pin 79 strappin g option is used to defeat it. ma [ 10:0 ] 32 , 31 , 34-36 , 40-42 , 44 , 49 , 50 o memory address signal ma10 to ma0 and peripheral power control signals: for dram c y cles , these are ma addresses. for isa bus c y cles ( atcyc# low ) : 1 ) ma [ 11:0 ] are peripheral power control pins latched externall y with si g nal ppwrl; 2 ) ma [ 9:6 ] are decoded b y aen and atcyc# low to become pro g rammable chip select si g nals csg1# , csg0# , csg3# , and csg2# respectivel y . 82C465MV/mva/mvb opti ? pa g e 26 912-3000-016 revision: 3.0 3.7.4 l2 cache interface 3.7.5 isa bus interface signal name pin no. signal type selected by signal description drty 197 i/o this interface is onl y avail- able if the pin 146 strap option ( see table 3-2 ) is set. dirty bit beoe# 196 o cache output enable, even booe# 195 o cache output enable, odd ecawe# 194 o cache write enable, even ocawe# 193 o cache write enable, odd tagwe# 192 o tag ram write enable eca2 191 o cache ca2 eca3 190 o cache ca3 tag [ 7:0 ] 199 , 202- 207 , 2 i/o tag ram data tagcs# 189 o tag ram chip select ccs0-3# 23 , 13 , 3 , 198 o cache chip select 0-3 sdir 149 o sd[15:0]-to-cd[31:16] buffer direction control sdenh# 104 o sd[15:8]-to-cd[31:24] buffer enable sdenl# 89 o sd[7:0]-to-cd[23:16] buffer enable signal name pin no. signal type selected by signal description sd [ 15:0 ] 91-95 , 98- 103 , 106-110 i/o isa bus data sd15 to sd0 atclk 155 o isa bus clock bale 162 o isa bus address latch mrd# 154 i/o isa bus memory read command mwr# 153 i/o isa bus memory write command iord# 152 i/o isa bus i/o read command iowr# 151 i/o isa bus i/o write command chrdy 150 is/od isa bus channel ready m16# 159 is/o 16-bit memory slave: this isa bus si g nal indicates a 16- bit memor y slave is respondin g . normall y an input , this si g - nal becomes an output when a master accesses local memor y . io16# 178 is 16-bit i/o slave: this isa bus si g nal indicates a 16-bit i/o slave is respondin g . 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 27 revision: 3.0 3.7.6 ipc (82c206) interface sa [ 1:0 ] 148 , 146 strap option pins , refer to table 3-2 i/o isa bus address sa1 to sa0: provide the remainin g two sa bus address lines , which cannot be buffered directl y from the cpu ca bus. sbhe# 161 strap option pin , refer to table 3-2 i/o system byte high enable: indicates a transfer on the upper b y te of the isa data bus sd [ 15:8 ] . dwr# o drive write: provides write command for local-bus ide c y cles when q ualified b y dbe. rfsh# 145 i/o refresh: indicates isa bus refresh c y cles. lmegcs# + atcyc# 160 strap option pin , refer to table 3-2 o lower memory chip select and isa i/o cycle indica- tor: this si g nal is active when the memor y c y cle address is below 1mb. it is used to g enerate smrd# and smwr#. for isa bus i/o c y cles , it is used to g enerate csg0-3#. chck# 179 is isa bus channel check: provides the s y stem with parit y information about memor y or devices on the isa bus. it indicates a non-correctable s y stem error and is one of the sources used to g enerate a cpu nmi. kbcrstin is syscfg 79h [ 2:1 ] = 11 ( mva ) keyboard controller reset input: chck# can be recov- ered on epmi4 ( mvb ) . internall y s y nchronized to hlt to g enerate cpurst with the correct timin g . signal name pin no. signal type selected by signal description signal name pin no. signal type selected by signal description rqmx3 81 is multiplexed input signals of drq1, drq3, drq6, drq7 rqmx2 82 is multiplexed input signals of irq10, drq0, drq5, irq15 rqmx1 83 is multiplexed input signals of irq6, irq8, irq4, irq12 rqmx0 84 is multiplexed input signals of irq3, irq1, irq7, irq14 irq11 85 i interrupt request channel 11 irq9 86 i interrupt request channel 9 irq5 87 i interrupt request channel 5 dreq2 88 i syscfg a1h [ 5 ] = 0 dma request channel 2. epmmux i syscfg a1h [ 5 ] = 1 epmi input mux dack2# ( 486 ) 80 o syscfg a0h [ 5 ] = 0 dma channel two acknowledge (486 mode, 386 mode option) npint ( 386 ) o numeric processor interrupt (386 mode) lgnt# o syscfg a0h [ 5 ] = 1 local bus grant 82C465MV/mva/mvb opti ? pa g e 28 912-3000-016 revision: 3.0 3.7.7 pmu interface memor y con- trols ( normal ) 79-77 strap option pins , refer to table 3-2 o memory control lines: refer to section 4.4 , "dram controller" on pa g e 48 dackmux0- 2 ( if mem. con- trols are defeated ) o encoded dack0-7# signals (463-compatible solution): available here onl y if memor y controls interface is defeated throu g h pin 79 strap option. connect to 74138 decoder to derive dack0#-dack7# ( dack4# not valid ) . note that pins 77-79 are on cpu i/o power plane and ma y be 3.3v si g nals. epmi pins ( default ) 163 , 185 , 184 i syscfg a0h [ 3 ] = 0 lowbat, epmi2, epmi1 interface (at power on default): refer to section 4.7 , "power management unit" on pa g e 103 for full details. dackmux0-2 o syscfg a0h [ 3 ] = 1 encoded dack0-7# signals (preferred solution for new designs): available here onl y if syscfg a0h [ 3 ] = 1. epmi si g nals must be relocated to an external multiplexer. connect to a 74138 decoder to derive dack0#-dack7# ( dack4# not valid ) . note that these pins are on the at i/o power plane and ma y be 5.0v si g nals. tc/drd# 175 o isa bus terminal count/drive read: provides read command for local bus ide when q ualified b y dbe#. aen 170 o isa bus address enable: indicates that the dma control- ler has taken control of the cpu address bus and the isa bus command lines. signal name pin no. signal type selected by signal description signal name pin no. signal type selected by description lowbat 163 i syscfg a0h [ 3 ] = 0 low battery indication: has pro g rammable polarit y : syscfg 40h [ 4 ] . dackmux0 i syscfg a0h [ 3 ] = 1 dackmux0: see section 4.6.3 , "integrated peripheral controller" on pa g e 76. llowbat 182 i syscfg a0h [ 3 ] = 0 very low battery indication: has pro g rammable polarit y : syscfg 40h [ 5 ] . pmimux i syscfg a0h [ 3 ] = 1 epmi multiplex input: refer to section 3.4 , "program selected interface options" on pa g e 9. epmi1 184 i syscfg a0h [ 3 ] = 0 external pmi source one: has pro g rammable polarit y : syscfg 40h [ 1 ] . dackmux2 i syscfg a0h [ 3 ] = 1 dackmux2: see section 4.6.3 , "integrated peripheral controller" on pa g e 76. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 29 revision: 3.0 epmi2 185 i syscfg a0h [ 3 ] = 0 external pmi source two: has pro g rammable polarit y : syscfg 40h [ 2 ] . dackmux1 o syscfg a0h [ 3 ] = 1 dackmux1: see section 4.6.3 , "integrated peripheral controller" on pa g e 76. rsmrst# o pin 148 strap option ( see table 3-2 ) resume reset susp/rsm 183 i suspend/resume: indirect suspend source ( can cause smi to initiate suspend ) ; direct resume source ( cannot be disabled ) . tris# 176 strap option pin , refer to table 3-2 o suspend mode indication (no ide): a '0' indicates that the s y stem is in suspend mode. dbe o data buffer enable (ide enabled): enables the com- mand line buffer to the ide interface. refer to the ide interface section. pio0 ( no master ) 174 i/o syscfg a0h [ 5 ] = 0 user definable i/o pin pio0 lreq# ( vl- bus master ) i/o syscfg a0h [ 5 ] = 1 local bus master request pio1 173 i/o syscfg 66h [ 1 ] = 0 user definable i/o pin pio1 nows# i syscfg 66h [ 1 ] = 1 isa bus zero wait state: option available when cmd# o syscfg f8h [ 0 ] = 1 compact isa command: this si g nal g enerates isa-like command timin g to the cisa peripheral devices. pio2 172 i/o syscfg 66h [ 2 ] = 0 user definable i/o pin pio2 cpuspd o syscfg 66h [ 2 ] = 1 cpu full speed indicator: a '1' indicates that the cpu is operatin g at full speed. atclkin i syscfg a0h [ 1 ] = 1 at clocking source input sabufen# o syscfg 79h [ 3 ] = 1 ( mva ) sa bus buffer enable: allows ca-to-sa bus buffer to be tristated when not in use to save power. pio3 171 i/o syscfg 66h [ 3 ] = 0 user definable i/o pin pio3 stpgnt# i syscfg 66h [ 3 ] = 1 cpu stop clock grant signal ppwrl 188 o peripheral power control signal latch: this si g nal is used to control the external latchin g of the peripheral power control si g nals ppwr11-0 from ma [ 11:0 ] . this si g - nal is pulsed durin g reset to pre-set the external latch. signal name pin no. signal type selected by description 82C465MV/mva/mvb opti ? pa g e 30 912-3000-016 revision: 3.0 3.7.8 miscellaneous signal interface master# 186 i isa bus master: note: master# is internall y decipher- able and need not be input. this pin should alwa y s be pro- g rammed as ri#. ri# i syscfg f8h [ 0 ] = 0 ring indicator: when the cisa interface is not needed ( syscfg f8h [ 0 ] = 0 ), this pin becomes the ri input and can be used to resume the s y stem after entr y to suspend mode. sel#/atb# + clkrun# i syscfg f8h [ 0 ] = 1 compact isa select. the cisa peripheral device ( usuall y the 82c852 ) asserts sel# to claim a cisa c y cle after decodin g its address on ale active. the 82C465MVb can optionall y inhibit the isa command lines when it receives sel#. at backoff. the cisa peripheral device asserts atb# between c y cles to g enerate an interrupt on the 82C465MVb. clock run. the cisa peripheral device asserts clk- run# to restart atclk when the 82C465MVb has issued a stpclk broadcast c y cle and stopped atclk. signal name pin no. signal type selected by description signal name pin no. signal type selected by description a20m# 130 o pin 198 strap option ( see table 3-2 ) a20 mask control (486 mode) ga20 i/o gated a20 line (386 mode): can be forced to a20m# function. rtcas 168 o rtc address strobe: this si g nal is active when the s y s- tem accesses port 70h. spkd 177 o speaker signal. uses special protocol when cisa is enabled. romcs# 90 o pin 146 strap option ( see table 3-2 ) rom chip select (no l2 cache mode): for memor y c y cles in the proper ran g e , this is the rom chip select. romcs# + rtcd# o rom chip select and rtcd# signal (l2 cache mode): combined si g nals. valid as rtcd# onl y when aen is low. rtcd# 89 o pin 146 strap option ( see table 3-2 ) real time clock (rtc) data strobe qualifier (no l2 cache mode): for i/o c y cles at port 70h , this is used to g enerate the rtc data strobe and read/write si g nal. sdenl# o l2 cache control signal (l2 cache mode): refer to l2 cache interface section of this table. kbdcs# 104 o pin 146 strap option ( see table 3-2 ) keyboard controller chip select (no l2 cache mode): this si g nal is q ualified with aen to produce the ke y board chip select. sdenh# o l2 cache control signal (l2 cache mode): refer to l2 cache interface section of this table. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 31 revision: 3.0 3.7.9 power and ground pins xdir 149 o pin 146 strap option ( see table 3-2 ) xd bus data buffer direction control: a '1' indicates data transfer from the 82C465MV sd bus to the xd-bus device. normall y hi g h , it is low for the followin g two condi- tions: 1 ) when romcs# and mrd# are both active , and 2 ) durin g reads from i/o ports 060h , 064h , 070h , and 071h. sdir o l2 cache control signal: refer to l2 cache interface section of this table. signal name pin no. signal type selected by description name type pin no description vdd cpu i/o power 1 , 43 , 53 , 114 , 201 +3.3v vdds at i/o power 97 , 147 , 165 +5.0v vddcore core v cc power 10 , 61 , 157 same as vdds gnd gnd 15 , 26 , 38 , 52 , 60 , 71 , 96 , 105 , 119 , 142 , 156 , 164 , 200 , 208 ground 82C465MV/mva/mvb opti ? pa g e 32 912-3000-016 revision: 3.0 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 33 revision: 3.0 4.0 functional description 4.1 463/465 chipset programming comparison man y opti chipsets are desi g ned to be re g ister-compatible with their immediate predecessors. in the case of the 82C465MV , virtuall y all of the pro g rammin g re g isters in the 82c463mv are directl y available. however , certain 82c463mv features have been superseded b y new 82C465MV re g isters. in such cases , onl y the recom- mended re g isters have been documented here. pro g ram- mers can refer to the 82c463mv data book for information on older re g isters , but are discoura g ed from usin g non cur- rent re g isters. the reason for this is that in the eventual suc- cessor to the 82C465MV , certain 82c463mv re g isters ma y no lon g er be available. code desi g ned to accommodate both the 82c463mv and 82C465MV to determine the chipset t y pe should read the product indicator syscfg 30h [ 7:6 ] ( see table 4-1 ) . table 4-1 product indicator register bit 4.2 cpu and vl-bus interface the 82C465MV chipset is t y picall y used to support a cpu with a 32-bit 486-t y pe interface , but can also support 32-bit 386dx-t y pe interfaces. the standard cpu si g nalin g interface is provided and is known as the vesa local bus ( vl-bus ) . the full y featured vl-bus interface additionall y allows for connection of hi g h-speed peripheral devices such as the opti 92c178 local-bus lcd controller. this section describes the cpu interface as part of the total vl-bus support provided b y the 82C465MV chipset. all vesa-standard si g nals are provided either on dedicated pins or as options. 4.2.1 basic command interface the vl-bus interface uses a standard command interface whose function and timin g are described in cpu data books. the primar y si g nal interface involves three c y cle-t y pe si g nals: m/io# , w/r# , and d/c#; and a pair of c y cle start and comple- tion handshakin g si g nals , ads# and rdy#. both 386 and 486 interfaces use these si g nals. the 486 interface allows for read bursts ( multiple hi g h-speed se q uential read c y cles ) and therefore provides brdy# and blast# to control burst read c y cles. for the 486 interface , and for certain h y brid 386/486 inter- faces as well , si g nals ken# , ahold , eads# , and flush# are provided for cache control. 4.2.1.1 cycle signals the cpu interface provides three status si g nals to indicate c y cle t y pe for the current c y cle: m/io# , to distin g uish memor y accesses from i/o access; w/r# , to distin g uish writes from reads; and d/c# , to distin g uish data accesses from code fetches. all of these si g nals are valid for a g uaranteed amount of time before the cpu or vl-bus master sets its ads# si g nal active. the risin g ed g e of ads# ( when it g oes from active to inactive ) indicates that the ca bus address and the c y cle t y pe si g nals are valid. normall y, the 82C465MV samples the state of ads# accord- in g to the cpuclk si g nal. all of the c y cle t y pe si g nals are g uaranteed b y the cpu manufacturer to be valid for a certain amount of time from a cpuclk clock ed g e when ads# is active. therefore , if the 82C465MV lo g ic sees ads# low within this window it can determine the c y cle t y pe without actuall y waitin g for the risin g ed g e of ads#. this lo g ic improves performance dramaticall y, since a full cpuclk is saved on each cpu c y cle. 76543210 syscfg 30h control register 1 default = 40h 82c46x product indicator ( ro ) : 00 = 82c463/463mv 01 = 82C465MV 10 = 82C465MVa 11 = 82C465MVb 82C465MV/mva/mvb opti ? pa g e 34 912-3000-016 revision: 3.0 however , at hi g h bus speeds ( 40-50mhz ), the ads# si g nal ma y not alwa y s be s y nchronized as well with the cpuclk si g nal and onl y after the risin g ed g e of ads# will the control- ler lo g ic be g uaranteed to capture the correct c y cle bein g si g - naled. therefore , the 82C465MV lo g ic includes a control bit that allows the selection of whether the c y cle t y pe will sam- pled when ads# is seen low to improve performance , or whether ads# will be latched and the c y cle sampled on the next clock ed g e to g uarantee functionalit y . syscfg d1h [ 6 ] selects this functionalit y ( see table 4-2 ) and defaults to latch- in g ads# so that bootin g at an y speed will be possible. the bios should check for slower speed cpus and clear this bit if possible for better performance. 4.2.2 local device interface the 82C465MV allows vl-bus peripheral devices to share the local bus with the cpu and the numeric coprocessor. the performance of these devices , which ma y include the video controller , lan adapters , and other pc/at controllers , will dramaticall y increase when allowed to operate in this hi g h speed environment. these devices are responsible for their own address and bus c y cle decodin g and must operate prop- erl y at the elevated fre q uencies re q uired for the local cpu bus. 4.2.2.1 ldev# operation the ldev# input si g nal to the 82C465MV indicates whether a local-bus device will be respondin g to the current c y cle. if the access is not in the local dram ran g e and the 82C465MV samples ldev# active at the end of the first t2 clock c y cle , it will allow the respondin g device to assume responsibilit y for terminatin g the current local c y cle. other- wise , the 82C465MV passes on the c y cle to the isa bus. if the access is in the local dram ran g e , the 82C465MV lo g ic i g nores ldev#. normall y, if a local bus device asserts ldev# and then removes it without respondin g with its lrdy# , the 82C465MV will await a response forever and the s y stem will han g . syscfg adh [ 7 ], as shown in table 4-3 , is provided to avoid this situation. ignore unfinished ldev# cycles syscfg adh[7] - allows ldev# to be asserted to claim a c y cle for the local bus , but then allows the c y cle to be g iven up if no lrdy# ( rdyi# or rdy# ) is g enerated. when syscfg adh [ 7 ] = 0 and ldev# is sampled asserted , the lo g ic g ives up the c y cle to the local bus and awaits rdy# from the local device. if the local device never actuall y responds , the s y stem will han g . if syscfg adh [ 7 ] = 1 and ldev# is sampled asserted , the lo g ic g ives up the c y cle to the local bus and awaits rdy# as usual. however , if no rdy# is returned before ldev# g oes inactive , the chipset lo g ic takes back ownership of the c y cle and forwards it to the isa bus. table 4-2 ads# sampling control table 4-3 ldev# control 76543210 syscfg d1h l2 cache control register 2 default = 41h ads# samplin g : 0 = sample on ads# low 1 = latch ads#, sam- ple on next c y cle 76543210 syscfg adh feature control register 3 default = 00h i g nore unfinished ldev# c y cles: 0 = wait 1 = i g nore 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 35 revision: 3.0 note that there is no time-out when the i g nore unfinished ldev# c y cles option is selected. the 82C465MV chip will wait indefinitel y as lon g as ldev# remains active and no rdy# si g nal is returned. as soon as ldev# g oes inactive with no rdy# si g nal y et received , the 82C465MV takes back control of the c y cle. 4.2.2.2 lrdy# operation when the local bus device has completed its operation , it uses the vl-bus local read y si g nal lrdy# to terminate the c y cle. the lrdy# si g nal is defined in the vl-bus specifica- tion to be driven b y a tristate buffer. therefore , at bus speeds up to 33mhz , lrdy# can simpl y be tied directl y to the cpu rdy# input. above 33mhz , the vl-bus device ma y not meet the timin g re q uirements of cpu rdy#. in this case , lrdy# can be connected to the rdyi# input of the 82C465MV for re-s y nchronization to the cpu rdy# si g nal. the 82C465MV provides syscfg adh [ 0 ] to control whether the rdyi# input will be buffered to drive the cpu rdy# line directl y, or will be latched and s y nchronized to the cpu rdy# input on the next clock. refer to the numeric copro- cessor interface section of this document for information on this bit. 4.2.2.3 vl-bus arbitration logic the 82C465MV provides arbitration amon g the various s y s- tem resources: cpu , dma , vl-bus masters , isa bus mas- ters , and refresh lo g ic. durin g c y cles where the cpu is not the s y stem master , the 82C465MV asserts hold to the cpu. the cpu responds to an active hold si g nal b y g eneratin g hlda after completin g its current bus c y cle and placin g most of its output and i/o pins in a hi g h impedance state. after the cpu relin q uishes the bus , the 82C465MV responds b y issuin g the appropriate si g nal. ? for a refresh timer re q uest , the 82C465MV lo g ic runs a dram refresh c y cle and isa bus refresh c y cle. ? for a dma re q uest or master re q uest initiated b y assertion of one of the drq lines , the chip provides the correspond- in g dack# si g nal alon g with ior#+memw# or iowr#+memr#. ? for a vl-bus master re q uest indicated on lreq# , the chip responds with lgnt#. the isa bus controller in the 82C465MV arbitrates between hold and refresh re q uests , decidin g which will own the bus once the cpu relin q uishes control with the hlda si g nal. the arbitration between refresh and dma/masters is based on a fifo priorit y . however , a refresh re q uest ( rfsh# ) will be internall y latched and serviced immediatel y after the dma/master finishes its re q uest if q ueued behind hold. hold must remain active to be serviced if the refresh re q uest comes first. table 4-4 rdy# synchronization 76543210 syscfg adh feature control register 3 default = 00h rdyi# input: 0 = s y nchro- nized to rdy# 1 = direct 82C465MV/mva/mvb opti ? pa g e 36 912-3000-016 revision: 3.0 4.2.3 vl-bus masters the 82C465MV optionall y provides one set of lreq# and lgnt# si g nals to support bus masters. these si g nals are used in con j unction with devices such as the opti 82c832 vl-pci brid g e chip that must g ain ownership of the vl bus for certain bus a g ents. support for a sin g le bus master re q uest is ade q uate for most applications , since the pci subs y stem can often combine multiple master re q uests into the sin g le re q uest line avail- able. conse q uentl y, this solution will not limit the pci options if the 82c832 solution is chosen. the bus master support actuall y is provided on the vl-bus. therefore , an y vl-bus master can make use of these si g - nals. 4.2.3.1 hardware considerations enablin g bus master support re q uires that pin 80 , the dedi- cated dack2# si g nal , be replaced b y lgnt# , and that pin 174 ( pio0 ) be replaced b y the lreq# input from the vl-bus. dack2# is alwa y s available on the dack decoder ( decodin g dackmux0-2 ), so onl y pio0 is lost and no additional ttl is re q uired. 4.2.3.2 programming the vl-bus master support feature is enabled b y settin g syscfg a0h [ 5 ] = 1 ( see table 4-5 ) . dack2# is alwa y s available on dack decoder , re g ardless of the settin g of this bit. 4.2.4 data bus conversion/data path logic the 82C465MV performs data bus conversion when the cpu accesses 8- or 16-bit devices throu g h 16- or 32-bit instruc- tions. it also handles dma and master c y cles that transfer data between local dram or cache memor y and locations on the isa or vl-bus. 4.2.4.1 cpu data bus multiplex option when the s y stem desi g n includes an external writeback cache , the si g nal pins normall y used for the upper 16 lines of the cpu data bus are converted to cache ta g data and con- trol si g nals. conse q uentl y, the 82C465MV must use an exter- nal 16-bit buffer to move data between cd [ 31:16 ] and sd [ 15:0 ] for isa bus operations and internal re g ister accesses. this external buffer is controlled b y three si g nals: sdenh# , sdenl# , and sdir , that control a 16-bit '245-t y pe buffer. if the cpu interface operates at 3.3v and the isa bus at 5.0v , this buffer must translate the level. the control si g nals men- tioned will alwa y s be at the level of the vcc supplied to isa i/o pads , which is appropriate for all standard desi g ns. also when the external writeback cache is used , the xdir si g nal is redefined and must be derived from iow# , memr# , and the chip selects of all devices on the xd bus. table 4-5 bus master enabling 76543210 syscfg a0h feature control register 1 default = 00h enable local bus master support: 0 = pio0 and dack2# 1 = lreq# and lgnt# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 37 revision: 3.0 4.2.5 numeric coprocessor interface the 82C465MV monitors ferr# and npbusy# to provide support for the 80387 coprocessor ( npx ) when the chipset is strapped for an 80386-t y pe interface. there are no provisions for an external coprocessor when a 486sx cpu is used. 4.2.5.1 hardware considerations the npx asserts ferr# durin g a power-on reset to indicate its presence. if the 82C465MV lo g ic senses ferr# low when it asserts npurst , it automaticall y g enerates ldev# to itself whenever ca31 is hi g h for a c y cle. this feature allows the coprocessor to g enerate its own rdy# to the cpu. the auto- matic co-processor reco g nition feature can be disabled throu g h syscfg adh [ 1 ] . the 82C465MV treats an y access to the npx address space as an at c y cle if the npx is not installed , and g enerates its own rdy# to the cpu at the end of the at c y cle. note that a vl-bus device can also respond with ldev# to claim the c y cle , and is responsible for g eneratin g lrdy# ( rdy# ) to the cpu. when the npx has completed its c y cle , the npx rdy# si g - nal terminates the c y cle b y assertin g : 1. cpu rdy# with a fast open-collector driver controlled b y the npx rdy# si g nal ( not g enerall y a practical option to implement ) 2. rdyi# to the 82C465MV , which latches it and drives its rdy# output to the cpu low on the next clock ( syscfg adh [ 0 ] = 0 ) 3. rdyi# to the 82C465MV , which drives its rdy# si g nal to the cpu low on the same clock ( syscfg adh [ 0 ] = 1 ) . the coprocessor asserts npbusy# while executin g a float- in g -point calculation and asserts rdyi# to the 82C465MV when it is finished. if npbusy# is active and a co-processor error occurs ( co-processor asserts ferr# ), the 82C465MV latches npbusy# and g enerates irq13. latched busy# and irq13 is cleared b y a write command to i/o port 0f0h. the rdyi# input is a strap-selectable option on the 82C465MV interface. refer to the section 3.3 "strap- selected interface options" for details on enablin g the rdyi# input. 4.2.5.2 programming the rdyi# pin option must first be selected b y strappin g as noted above. once rdyi# is available , it can function either as a direct input to the cpu rdy# si g nal or as a latched , dela y ed input , accordin g to the settin g of syscfg adh [ 0 ] . syscfg adh [ 1 ] provides a means for overridin g automatic co-processor detection if desired. the re g ister at syscfg adh is described next and shown in table 4-6. 4.2.6 special cpu interface support certain cpus operate internall y with '486-t y pe lo g ic , y et present a '386 or '386/'486 h y brid si g nal interface. the ibm blue li g htnin g processor uses this t y pe of interface. the 82C465MV lo g ic provides special features to handle mixed interfaces. 4.2.6.1 ability to cut cpu power during suspend the 82C465MV will condition its outputs durin g suspend accordin g to whether the connected cpu can be placed in a low-power mode durin g suspend , or can simpl y be powered down completel y . the affected si g nals are listed in section 3.6 "pin signal characteristics" . the 82C465MV reset lo g ic g enerates a cpurst on exitin g from suspend mode when this option is selected. the option of complete cpu power-down on suspend is selected b y writin g bit adh [ 5 ] = 1. 4.2.6.2 programmable a20m# functionality strappin g the 82C465MV to provide a '386 interface automat- icall y switches the function of pin 130 from a20m# to ga20. however , certain h y brid interface cpus re q uire a 386 inter- face with an a20m# input. the 82C465MV is pro g rammable to force a20m# operation re g ardless of the interface selected. this option is enabled b y writin g syscfg adh [ 4 ] = 1. table 4-6 special cpu feature programming bits 76543210 syscfg adh feature control register 3 default = 00h i g nore unfinished ldev# c y cles: 0 = wait 1 = i g nore generate cpurst immediatel y ? 0 = no 1 = yes (mva) cpu power state in suspend: 0 = powered 1 = 0 volt pin 130 in 386 mode: 0 = ga20 1 = a20m# sreset operation: 0 = normal 1 = to gg le on resume pin 80 in 386 mode: 0 = npint 1 = dack2# coprocessor reco g nition: 0 = enable 1 = override rdyi# input: 0 = s y nchro- nized to rdy# 1 = direct 82C465MV/mva/mvb opti ? pa g e 38 912-3000-016 revision: 3.0 4.2.6.3 programmable cpu reset functionality pro g rammable reset functionalit y allows a cpu powered- down durin g suspend to restart operation on resume. the 82C465MV provides both soft and hard resets on sreset whenever it is strapped for '386 interface operation. the reset input to h y brid-interface cpus must be connected to the 82C465MV sreset si g nal for proper operation. this reset option is enabled b y writin g syscfg adh [ 3 ] = 1 before the first software- g enerated reset occurs. operation is then as follows. the cpu has its power cut after enterin g suspend mode ( usin g the ppwr0 power control latch si g nal to control the power mosfet for the cpu ) . on resume , the ppwr0 line will turn on the cpu first. then after the pro- g rammable dela y associated with ppwr0 , the sreset line will be driven hi g h to reset the cpu. note that this arran g ement provides the vl-bus with an inde- pendent reset si g nal , cpurst , so that vl-bus peripheral devices need not be inadvertentl y reset on a q uick resume c y cle. the onl y important consideration in this t y pe of arran g ement is the software scheme. the smm code that initiates the sus- pend operation must save the complete cpu context and be capable of restorin g it without lapsin g into a complete s y stem reboot. 4.2.6.4 programmable dack2# functionality strappin g the 82C465MV to provide a '386 interface automat- icall y switches the function of pin 80 from dack2# to npint , re q uirin g s y stem desi g ns to use dack2# from the dack decoder. however , since npint serves no purpose for most s y stems , man y desi g ners would prefer to keep the dedicated dack2# si g nal. the 82C465MV is pro g rammable to force dack2# operation re g ardless of the interface selected. this option is enabled b y writin g syscfg adh [ 2 ] = 1. note that this bit settin g is i g nored if pin 80 is used for lgnt# ( syscfg a0h [ 5 ] = 1 ) ; the lgnt# function alwa y s takes pri- orit y . 4.2.6.5 cyrix linear burst mode support next- g eneration c y rix m1sc cpus provide a performance improvement throu g h an optional linear wrap mode burst. the 82C465MVb part supports this feature throu g h syscfg 3fh [ 7 ] ( see table 4-7 ) . since the c y rix cpu defaults to an intel-compatible mode at power-up , the s y stem can boot without problems. 4.2.6.6 programmable exclusion of coprocessor recognition the 82C465MV automaticall y reco g nizes the presence of an external co-processor in a '386-t y pe s y stem b y lookin g for an active ferr# line at reset time. if ferr# is sampled low at reset , an y i/o c y cle with a31 hi g h automaticall y g ets for- warded to the vl-bus and the 82C465MV lo g ic will not pro- vide rdy#. for special desi g ns in which this arran g ement conflicts with other devices mapped in hi g h i/o space , the 82C465MV local-bus lo g ic can be pro g rammed to alwa y s pass these c y cles throu g h to the isa bus and g enerate rdy# to the cpu. this feature is enabled b y writin g syscfg adh [ 1 ] = 1. 4.2.6.7 programmable rdyi# functionality the 82C465MV normall y takes the rdyi# input , s y nchro- nizes it throu g h a flip-flop , and combines it with other sources to g enerate the open-collector rdy# si g nal to the cpu. this feature is provided for devices that cannot meet cpu rdy# setup times or cannot tristate their rdy# output after drivin g it inactive. the process effectivel y inserts a wait state and ma y reduce performance. timin g anal y sis indicates that the co-processor rdy# si g nal , for example , can be combined with cpu rdy# throu g h a fast tristate buffer and will meet the cpu rdy# setup re q uirement in man y s y stems. therefore , the 82C465MV is pro g rammable to inhibit rdyi# s y nchronization and simpl y pass rdyi# throu g h a tristate buffer to combine it with the existin g rdy# output line to the cpu. this feature can be used in con j unction with an exter- nal co-processor that provides a direct-drive coprocessor rdy# si g nal , such that when the 82C465MV reco g nizes a co-processor c y cle , it will route the rdyi# si g nal directl y to cpu rdy# and improve co-processor performance. this option is enabled b y writin g syscfg adh [ 0 ] = 1. this bit has no function unless sbhe# is pulled low at s y stem reset time to enable the rdyi# pin function. note that the co-processor rdyo# si g nal can also be tristate buffered externall y so that the rdyi#/ca25 input can be used in its ca25 capacit y for 64mb on-board dram support. table 4-7 burst mode setting 76543210 syscfg 3fh misc. control register default = 00h cpu burst mode: 0 = intel 1 = c y rix linear (mvb) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 39 revision: 3.0 4.3 system functions the 82C465MV handles clock g eneration , reset lo g ic , and other basic s y stem lo g ic functions as described in the follow- in g sections. 4.3.1 reset logic there are several si g nals involved in the 82C465MV s y stem reset lo g ic scheme. 4.3.1.1 rst1# a low si g nal on input rst1# causes a hardware reset. the s y stem must g enerate rst1# from the reset switch or from the power module si g nal representin g power g ood. this reset si g nal forces the s y stem to be g in execution in a known state. when rst1# is sensed active , the 82C465MV initiates a g eneral reset c y cle that lasts for 128 cpu clock c y cles on all reset outputs. 4.3.1.2 rst4# the rst4# output provides a peripheral reset si g nal that can be used to reset local devices directl y, and can be inverted to provide rstdrv to the isa bus. 4.3.1.3 cpurst and sreset the cpurst output provides a hard reset si g nal to the cpu , usuall y throu g h its reset input. the sreset output provides a soft reset si g nal to cpus that can accommodate this function. software g enerates reset b y writin g to the at- or ps/2-compatible command ports. a soft reset is much faster ( from the cpu perspective ) than a hard reset. the sreset si g nal duration is the same as that of cpurst. on the 82C465MV , sreset also g oes active dur- in g hardware resets in '386 interface mode. refer also to section 4.2.6 "special cpu interface support" for information on how the cpurst and sreset si g nals can be controlled durin g resume se q uences. 4.3.1.4 resume reset (rsmrst#) function the rsmrst# output supplies a reset si g nal onl y when resumin g from suspend mode that is used to restart devices that were powered down on enterin g suspend mode. rsmrst# is provided on ppwr10 of the power control latch. rsmrst# is optionall y available on pin 185 ( epmi2 ) as well. pin 148 strappin g works in con j unction with syscfg 40h [ 0 ] ( seetable 4-8 ) to determine the reset lines that to gg le upon resumin g from suspend mode. refer to section 3.3 "strap- selected interface options" for information on redefinin g pin 185 as rsmrst#. see fi g ure 4-1 for an illustration of the options. table 4-8 resume reset control 76543210 syscfg 40h pmu control register 1default = 00h rsmrst# select: 0 = disable 1 = enable see fi g ure 4-1 82C465MV/mva/mvb opti ? pa g e 40 912-3000-016 revision: 3.0 figure 4-1 resume reset function case 1: rst4# sa1 ( pin 148 ) pulled hi g h syscfg 40h [ 0 ] = 0 case 2: rst4# sa1 ( pin 148 ) pulled hi g h syscfg 40h [ 0 ] = 1 case 3:* rst4# sa1 ( pin 148 ) pulled low syscfg 40h [ 0 ] = 0 case 4:* rst4# sa1 ( pin 148 ) pulled low syscfg 40h [ 0 ] = 1 rst4# epmi2/rsmrst# ppwr10/rsmrst# rst4# epmi2/rsmrst# ppwr10/rsmrst# rst4# ppwr10/rsmrst# rst4# ppwr10/rsmrst# power-on resume * for cases 3 and 4 , sa1 ( pin 148 ) pulled low causes epmi2/rsmrst# to have the function epmi2 and is an input. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 41 revision: 3.0 4.3.1.5 rapid reset generation the 82C465MV will monitor commands to i/o ports 060h and 064h , and intercept certain commands to port 060h , so that it can rapidl y emulate the ke y board controller g eneration of the software reset si g nal. the decode se q uence is software- transparent and re q uires no bios modifications to function. the 82C465MV lo g ic rapidl y g enerates a fast cpu warm reset function when it detects a write of value feh to port 064h , or a value of 1 to bit 0 of i/o port 092h. note: fast reset ( ports 092h and 064h emulation ) is g ener- ated on sreset for the intel sl enhanced or the c y rix cx486s/s2 cpus ( ccs0# , pin 23 and ccs1# , pin 13 , both strapped hi g h ) and on cpurst for other cpus. port 092h is implemented in the lo g ic accordin g to the re g is- ter la y out shown in table 4-9. fast reset control (port 092h or 064h) syscfg 30h[1] - settin g syscfg 30h [ 1 ] = 0 re q uires a halt instruction before g eneration of cpurst ( sreset if intel sl enhanced cpu ) . settin g syscfg 30h [ 1 ] = 1 allows the reset to occur immedi- atel y without a halt instruction. 4.3.1.6 fast reset handling in smm in normal operatin g mode , fast reset i/o commands to the ke y board controller ports 060h and 064h are intercepted and handled b y the 82C465MV lo g ic. the ke y board control never receives kbdcs# and therefore does not know the fast reset status. in smm , however , the 82C465MV lo g ic does not inhibit kbdcs#. therefore , a read of the ke y board controller ports to determine fast reset status will return the invalid sta- tus contained in the ke y board controller. therefore , port 092h should alwa y s be used to determine the fast reset settin g . port 092h returns the current settin g of both of the fast reset sources ( port 092h and port 060/064h ) . note that g eneration of sreset durin g smm is prohibited on intel and some other processors. writin g syscfg a0h [ 2 ] = 1 ( see table 4-11 ) inhibits g eneration of sreset durin g smm. table 4-9 system control port a (ps/2 compatibility port) table 4-10 controlling fast reset table 4-11 inhibition of sreset in smm 76543210 port 092h system control port a don't care alternate fast gate a20 ( r/w ) : 0 = no action 1 = set gate a20 active alternate fast reset ( r/w ) : 0 = no reset 1 = set reset active 76543210 syscfg 30h control register 1 default = 40h fast reset: 0 = wait for hlt 1 = immediatel y 76543210 syscfg a0h feature control register 1 default = 00h allow sreset in smm: 0 = enable 1 = disable 82C465MV/mva/mvb opti ? pa g e 42 912-3000-016 revision: 3.0 4.3.2 system clock generation the 82C465MV chipset re q uires a minimum of three input clocks. these clocks are used to g enerate output clocks and to time internal operations as described below. 4.3.2.1 input clocks oscclk. oscclk is the main input clock from which cpu- clk , fbclkout , lclk , and possibl y atclk are derived. its fre q uenc y is determined b y the cpu as follows. ? if a 2x cpu is bein g used , oscclk is re q uired to be 2x. pin 3 ( ccs2# ) must be sensed hi g h at reset ( as described in section 3.3 "strap-selected interface options" ) to indi- cate this condition. for example , a 33mhz 486dx , 2x clock cpu would re q uire a 66mhz input on oscclk. the pin 160 strap option , which indicates whether the input clock is 1x or 2x , must indicate 2x clock ( not pulled hi g h ) when pin 3 indicates a 2x cpu ( pulled hi g h ) . ? if a 1x cpu is bein g used , oscclk can be either a 1x or a 2x clock. pin 3 must be sensed low at reset ( pin 3 has an internal pull-down resistor at reset time so no external resistor is needed ) to indicate a 1x cpu. with pin 3 low , oscclk can be 1x or 2x as selected b y pin 160. - if pin 160 is sensed hi g h at reset time , oscclk is 1x. pin 160 must be pulled up b y a 10k w resistor if a 1x external clock is provided. - if pin 160 is sensed low , oscclk is 2x. an internal pull-down resistor is en g a g ed at reset time on pin 160 so no external strap is needed. when a 1x cpu is used with a 2x input clock , the 2x clock is simpl y divided and the resultin g 1x clock is passed on to the lo g ic as if the 1x clock had been input directl y . none of the internal 82C465MV lo g ic uses the 2x input clock in this con- fi g uration. with a 1x cpu , a 1x input clock is recommended to save power. osc14. the osc14 clock input ( from a 14.31818mhz source ) is used primaril y for the s y stem timer to retain isa compatibilit y . most s y stems will also buffer the source of this clock and pass it on to the isa bus as the osc14 si g nal to expansion devices. no s y nchronization to other s y stem clocks is re q uired. the 82C465MV confi g uration syscfg 43h [ 3:0 ] can select the osc14 si g nal ( or other clocks ) as the clock source for timin g isa bus c y cles. the selection provides osc14 divided b y two for an effective at clock rate of 7.2mhz as a close approximation of the 8mhz bus speed of the ori g inal isa bus. the kbclk and kbclk2 si g nals are derived from osc14. their use is described in the section below. atclkin. the atclkin option is selected throu g h syscfg a0h [ 4 ] . if selected , the desired base clock is input on pin 172 ( pio2 ) . this clock allows the isa bus clockin g to be derived from an y external input fre q uenc y . for example , if 8.0mhz isa bus operation is desired , atclkin must be an y multiple of 8mhz. 24mhz is often available and is commonl y used for this function. sqwin. the sqwin si g nal should alwa y s be runnin g, even in suspend mode. the clock input to sqwin is used to: ? time periodic dram refresh re q uests , both in active mode and , if enabled , in suspend mode ? decrement the s y stem activit y counters ( sqwin is divided b y pro g ram-selected values first ) ? control the sample rate of certain power mana g ement input pins ?to g enerate the kbclk and kbclk2 multiplexer clocks when no 14mhz source is available. the sqwin clock input can be 32khz or 128khz as selected b y syscfg 40h [ 3 ] . table 4-12 atclkin enabling and sqwin frequency bits 76543210 syscfg a0h feature control register 1 default = 00h pin 172 function: 0 = pio2 ( or cpuspd ) 1 = atclkin syscfg 40h pmu control register 1default = 00h sqwin fre q uenc y : 0 = 32khz 1 = 128khz 8 2 c 4 65mv/mva/mvb opti ? 9 1 2 - 3 0 0 0 - 0 16 p a g e 43 r e v i s i o n : 3 .0 4 . 3 . 2 . 2 ou t pu t c l ocks t h e 8 2c465mv ch i pse t pr o v i des s i x c l ock ou t pu t s . i t c a n c on t ro l p o w e r c ons u m p t i on b y ad j u s t i ng ma n y o f t hes e ou t put c l o c k f r e q ue n c i es dy nam i ca l l y as demand ch a ng es. fbclkout a n d cpuclk. t h e c l ock i np u t oscclk i s us e d to g en e ra t e s i g na l s fbclkout an d cpucl k . cpuclk i s 2 x fo r a 2 x cpu an d 1x f o r a 1x cpu . fbclkout i s a l wa ys 1x. cpuclk m a y b e di v i d ed i n t e rn a l l y u s i n g p r og r a mmab l e d i v i d e r a te s t o p r ov i d e powe r c o nt r o l o f t h e cpu an d t h e 8 2 c465mv ch i p s et . w h enev e r cpuclk i s d i v i de d , fbclk- out i s di v i d ed as we l l t o ma i n t a i n pr o per s i gn a l s y nch r on i za- t i on . t h e two c lo c ks c a n be d i v i ded t o ach i ev e a s l o wer f u l l- s pee d c l oc k a n d s av e s y s t em p o w e r . t h e y can a l so be au t o- ma t i ca l l y s low e d dow n (n o s o f t wa r e i n t e r ven t i o n r e q u i r e d ) d u r i ng pe r i ods o f low a c t i v i t y b y t h e h a r d w a r e d o z e m o de f ea t u r e d e sc r i b ed in t h i s d o cumen t . ? f b c l k o u t is t h e s y s t em c l o c k a n d i s f e d bac k i n t o p in fbc l kin to p r ov i de a s y n c hr o ni z e d c l oc k f o r mos t o f th e 8 2 c465mv in t e r na l c i r cu i t r y. ? cpuclk i s t he c l ock t o th e cpu . i n a dd i t i on t o be i n g ab l e t o d i v i de th i s c l oc k , t h e l o g i c c a n s to p cpucl k c o m p l e t e l y ( know n a s t h e s t op - cl o c k f e at u r e ) b y w ri t i n g a reg i s t e r b it. i t w i l l be r e st a r t ed au t oma t i c a l l y when t he 82c 4 65mv l o g i c d e te c t s a n i n t e r r up t e v en t s u c h a s irq , sm i , o r epm i . no t e t h at fbclkout i s not stopped when cpuclk is s to p ped. c l ock pha s e. b o th fbclkout a n d cpuclk m u st b e kept i n c l o se p has e a l i g n m e n t w i th e a c h o t h e r ; o t h e r w i s e , t h e 8 2 c465mv c y c l e co n t r o l le r m a y n ot samp l e t he cp u c o nt r ol l i nes at t h e a p pro p r i a t e t i m e . c l o c k p h ase a l i g n m e n t i s a f f e c t ed pr i mar i l y b y b oa r d l ay o u t and cp u t y pe . t he p ro v i- s io n fo r an e x te r na l f e edba c k c l oc k ( fbclkout i s f ed back to f b c l k i n ) al l o ws an y s k ew t o b e compen s a t ed f o r e x act pha s e a l i gnmen t . us u a l l y , a s er i es r es i s t or o r sma l l i nd u ct o r i n s e r i es w i t h e i t he r t he cpu c l ock o r t he f eedb a ck c l oc k i s su f f i c i en t t o r ea l i g n t h e c l oc k s . howeve r , fo r c e r t a i n cpus and bo a rd l a yo u ts t h i s co r re c t i on i s no t su f f i c i en t and an ex t e r n a l de l a y mus t be in t r oduc e d. the 82c4 6 5m v l o g i c a l l o ws an in t e r na l g at e d e la y t o be pr o - g r a m me d o n ei t he r t h e c p u c lo c k l i n e o r t h e fe e dbac k cl o ck l i ne t h r o u g h s t rap p in g o p t i on s . th i s de l ay pr o v i des a coa r se ad j us t men t o f c l oc k skew ; f in e ad j us t men t ca n th e n be c o m- p l et e d u si n g d i s cr e te comp o nen t s a s desc r i bed abo v e. ? to de l a y fbclkout by app r ox i mat e l y 2n s : pu l l p i n 77 h i g h a t r e se t ( ca n b e st r ap p ed p e rmane n t l y w i t h 10k w to i s a b u s v c c ) ? to de l ay cpucl k b y a pp r ox i m a te l y 2n s : pu l l p i n 7 8 l o w at r ese t ( can b e st r app e d pe r manen t l y w i th 10k w to g r ou n d). bo t h s t r ap s c a n b e u sed , but t end t o c ance l eac h o the r ou t . ex t er n al r e s i st o rs a r e n ot r e q u i re d t o d i s ab l e t h e de l ay s , as i n te r na l re s is t o r s ar e a c t i va t ed on p i ns 77 and 78 at r e se t . des i g ns sho u ld always include both strap options, e v en i f one or bo t h ar e l a t e r de e m e d u n nece s sa r y. lclk. lc l k c an be us e d to p r ov i de a 1x c l oc k f o r t he l o c a l bus . no r ma l l y, f bclkout i s u s ed t o p ro v i d e t he l o c a l bus c l ock , bu t lc l k c a n b e u se d i f fbclkou t i s t o o hea v i l y l o aded . lclk i s a l wa y s a 1x c l o c k, r e g a rd l es s of w h eth e r cpuclk i s 1 x o r 2x . howe v er , t he l clk p i n i s re d e f i ne d f o r l 2 cach e op e ra t i on , i n wh i c h ca s e fbclkou t mus t b e use d . atclk. t h e atclk i s used f o r t he i sa bus c l o c k. i t i s de r i v ed b y d i v i d i ng one of th r ee sou r ce s : fbclki n , osc1 4 , or a t clkin . the s our c e c l oc k and d i v i so r a r e se l e c t ed t h rou g h syscf g 4 3h [ 3: 0 ] ( re f e r t o ta b le 4 - 13 ) . i f atc l kin i s s el e ct e d , a su i t a b l e c l o c k mu s t be pr o v i ded o n p i o2 and syscfg a 0 h [ 4 ] m u s t be s e t to 1. ta b l e 4-13 a t clk rate s e l e c t ion 7 6 5 4 3 2 10 s y scfg 4 3h p m u c ontr o l r e gi s t e r 4 d e fa u lt = 0 0 h a t c l k g e n e r a t o r so u r c e : 0 = fbc l kin 1 = atc l kin w / sysc f g a 0 h [ 4 ] = 1 atc l k r a te s e l e c ti o n s : 0 0 0 = / 8 1 0 0 = 7 .2 m h z 0 0 1 = / 6 1 0 1 = / 2 0 1 0 = / 4 1 1 0 = / 1 ( / 2 i f s yscf g 4 3 h [ 3 ] = 0) 0 1 1 = / 3 1 1 1 = s top 82C465MV/mva/mvb opti ? pa g e 44 912-3000-016 revision: 3.0 to avoid the incompatibilities introduced because oscclk can be either 1x or 2x , the clock divisors are based on dou- ble the fbclkin clock. for example , whether oscclk is a 2x 66mhz clock or a 1x 33mhz , fbclkin is 33mhz and the isa clock divisors are based on double that value. therefore , selectin g fbclkin/8 would result in an 8.33mhz isa clock in this case. this rule holds true in all cases except for the divide-b y -1 settin g, which can onl y select the actual oscclk clock input. for example , usin g a 2x 66mhz oscclk , the divide-b y -1 isa clock is 66mhz; usin g a 1x 33mhz oscclk , the divide-b y -1 isa clock is 33mhz. note to 82c463mv programmers : pmu control re g ister 4 ( syscfg 43h ) chan g es sli g htl y from its 82c463mv imple- mentation , providin g additional isa clock divisor selections and a new isa clock source option. these features are pro- vided usin g reserved bits and selections , so that backward compatibilit y with 82c463mv software is maintained. table 4-14 indicates the appropriate atclk divisor settin g s for common input clock rates. atclk can automaticall y be stopped if there is no at bus activit y throu g h syscfg 5eh [ 2:1 ], as shown in table 4-15. kbclk and kbclk2. the clock output kbclk is provided for the ke y board controller. kbclk is also used alon g with kbclk2 ( kbclk divided b y 2 ) to provide clocks for multi- plexin g interrupt and dma re q uests. kbclk is 7.2mhz , and kbclk2 is 3.6mhz. when connected as the select inputs to 74153 multiplexers , the y select each of the four multiplexed inputs se q uentiall y once ever y 280ns. table 4-14 recommended divisor settings for various input clock frequencies * use 7.2mhz settin g if these speeds are too fast for at bus operations. table 4-15 at bus clock stretch controls fbclkin frequency doubled frequency used for divisor calculation /3 /4 /6 /8 12.5mhz 25mhz 8.1mhz 16mhz 33mhz 8mhz 20mhz 40mhz 6.6mhz 25mhz 50mhz 8.3mhz 33mhz 66mhz 8.25mhz 40mhz 80mhz 10mhz * 50mhz 100mhz 12.5mhz * 76543210 syscfg 5eh clock stretch register default = 00h atclk when not in c y cle: 0 = runs 1 = stopped at clock stretch: 0 = as y nc 1 = s y nc 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 45 revision: 3.0 4.3.3 a20m# generation the 82C465MV lo g ic provides both at-compatible and ps/2- compatible means of controllin g the a20m# si g nal to the cpu. ?a20m# g oes inactive ( hi g h ) if either the at-compatible port control is set to 1 ( b y writin g d1h to port 064h fol- lowed b y settin g port 060h [ 1 ] = 1 ) or the ps/2-compatible port control is set to 1 ( b y settin g port 092h [ 1 ] = 1 ) . ?a20m# g oes active if both the at-compatible port control and the ps/2-compatible port control are cleared to 0. the a20m# port control of port 092h is shown in table 4-16. a write to port 064h with data d0h will enable the status of gatea20 ( bit 1 of port 060h ) and the s y stem reset control ( bit 0 of port 060h ) to be readable in normal mode. 4.3.3.1 rapid a20m# generation the 82C465MV will monitor commands to i/o ports 060h and 064h , and intercept certain commands to port 060h , so that it can rapidl y emulate the ke y board controller g eneration of the a20m# si g nal. the decode se q uence is software-transparent and re q uires no bios modifications to function. the fast a20m# g eneration se q uence occurs when the cpu writes the value d1h to port 064h , followed b y writin g the value 02h to port 060h. the lo g ic inhibits kbdcs# on both the port 064h access and on the followin g port 060h access. therefore , the 82C465MV lo g ic can q uickl y switch its own a20m# line without waitin g for the ke y board controller to do so. the i/o write command and output data still g o to the sd and xd buses in both cases. table 4-16 system control port a (ps/2 compatibility port) 76543210 port 092h system control port a don't care alternate fast gate a20 ( r/w ) : 0 = no action 1 = set gate a20 active alternate fast reset ( r/w ) : 0 = no reset 1 = set reset active 82C465MV/mva/mvb opti ? pa g e 46 912-3000-016 revision: 3.0 4.3.3.2 inhibition of fast a20m# and fast reset generation due to a patent awarded a g ainst internal duplication of exter- nal ke y board controller functionalit y, s y stem desi g ners ma y prefer not to use the 82C465MV fast reset and fast a20m# g eneration features. therefore , the 82C465MVa part pro- vides the means to partiall y or completel y disable this mecha- nism. whether a s y stem desi g ner decides to use all , part , or none of the internal fast g eneration lo g ic depends on his interpretation of the patent with re g ard to the intended s y stem implementation. the 82C465MV part blocks kbdcs# g eneration when it detects certain data write se q uences to ports 060h and 064h , and g enerates the a20m# output or sreset output as appropriate. the 82C465MVa lo g ic can inhibit this fast g en- eration lo g ic at three different levels. 1. the lo g ic permits kbdcs# to pass throu g h re g ardless of whether it detects port 060/064h accesses. the chip continues to monitor port 060/064h accesses and g ener- ate a20m# and sreset. 2. the lo g ic permits kbdcs# to pass throu g h as above , but does not monitor port 060h/064h accesses to g ener- ate a20m# and sreset. internal port 092h accesses can still g enerate a20m# and sreset. the si g nals must be combined externall y with the si g nals g enerated b y the ke y board controller. 3. the lo g ic operates as in item 2 above. in addition , pin 179 is redefined as the kbcrstin input for the reset si g nal output from the ke y board controller. the lo g ic combines this control with the port 092h control as sources for sreset. pin 179 is normall y used as chck# , the isa bus nmi source; this option is lost when the pin is used as kbcrstin. the re g ister bits re q uired for these options are shown below , alon g with a new shadow re g ister for port 064h writes. table 4-17 fast signal generation control bits 76543210 syscfg 79h pmu control register 11 default = 00h fast lo g ic functionalit y level: 00 = full y functional 01 = do not inhibit kbdcs# 10 = also: disable reset from 060/064h 11 = also: redefine pin 179 as kbcrstin (mva) syscfg 9fh port 064h shadow register default = 00h - shadows i/o writes to port 064h bits [ 7:0 ] , re g ardless of whether kbdcs# is inhibited. in this wa y , when an smi occurs between a port 064h write and the subse q uent write to port 060h, smm code can access the ke y board controller as needed and then simpl y restore the port 064h value j ust before leavin g smm. (mva) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 47 revision: 3.0 4.3.3.3 a20m# handling in smm on entr y to smm , the a20m# si g nal is forced hi g h. the si g nal returns to its prior value on return to normal mode. writes to either a20m# control port are blocked while in smm. port 092h can be read at an y time , includin g smm. however , the gatea20 settin g cannot be read directl y from ports 060/064h while in smm. therefore , a read-onl y bit is pro- vided at syscfg a1h [ 7 ] to return the a20m# settin g at an y time. syscfg a1h [ 7 ] provides an indication of the gate a20 settin g last made throu g h the normal write se q uence at i/o port 060/064h. 4.3.3.4 port 060/064h a20m# setting accessibility on the 82C465MV and 82C465MVa parts , the port 060/064h a20m# settin g can be read in smm throu g h syscfg a1h [ 7 ] . this feature is important to zero-volt suspend ( suspend to disk ) because smm code must know the settin g of a20m# in order to restore the value after resumin g from a zero-volt suspend. the complementar y feature , however , is missin g from the mv and mva parts: there is no wa y to restore the port 060/064h bit settin g from within smm. therefore , resume code cur- rentl y has to restore the a20m# settin g from outside smm , which is not ver y clean. the 82C465MVb redefines syscfg a1h [ 7 ] to be writable as well as readable. when written as 0 , syscfg a1h [ 7 ] has no effect. when written as 1 , syscfg a1h [ 7 ] to gg les the cur- rent settin g of the port 060/064h a20m# bit. if smm code needs to restore a20m# to its ori g inal settin g, it simpl y reads syscfg a1h [ 7 ] to determine the current settin g, then writes back to syscfg a1h with bit 7 set to 1 if it is necessar y to to gg le the bit. software should then re-read syscfg a1h [ 7 ] to ensure that the bit has been restored to the desired value. table 4-18 a20m# read-only bit table 4-19 a20m# setting within smm 76543210 syscfg a1h feature control register 2 default = 00h port 060/4 gate a20 ( ro ) : 76543210 syscfg a1h feature control register 2 default = 00h port 060/4 gate a20 ( ro ) : in mvb, port 060/4 a20m# bit read: return current value; write: to gg le a20m# settin g 82C465MV/mva/mvb opti ? pa g e 48 912-3000-016 revision: 3.0 4.4 dram controller the 82C465MV uses an advanced memor y controller to g en- erate c y cles to five banks of s y mmetrical or as y mmetrical dram , mana g e the on-cpu writeback or write-throu g h cache ( l1 ), and mana g e an external writeback cache ( l2 ) . durin g dram read or write c y cles , a row address and a col- umn address is re q uired. in most drams , the row address access time is lon g er than the column address access time. therefore , bus performance can be improved b y usin g pa g e- mode dram operation. memor y locations sharin g the same row address are on the same pa g e; therefore , onl y a new col- umn address is re q uired. in pa g e mode operation , the row address strobe , ras# can be kept active and onl y a new cas# needs to be g enerated , thus reducin g memor y c y cle time. since the cas# lines are common for all the banks , onl y one bank can be kept active at a time. the effectiveness of pa g e- mode operation depends heavil y on the pa g e size. a lar g er pa g e size increases the chances of a pa g e hit. 4.4.1 dram controller hardware options the standard dram controller hardware includes direct con- trol of five banks of dram ( ras0#-ras3# ) and up to 12 bits of dram addressin g ( ma [ 11:0 ]) . throu g h relocation of cer- tain si g nals , certain of these features can be deleted to avoid usin g external ttl for external power mana g ement input si g - nals. refer to section 3.3 "strap-selected interface options" for information on the memor y interface selection options. the dram controller can also chan g e its decodin g accordin g to the s y mmetr y of the dram devices in use. the mappin g of the cpu address ( ca ) si g nals to the memor y address ( ma ) si g nals is controlled b y the followin g inputs. ? bank capacit y, as set b y bits [ 2:0 ] and [ 6:4 ] of syscfg a8h , a9h , and aah ?s y mmetrical or as y mmetrical dram selection , as set b y bits [ 3 ] and [ 7 ] of syscfg a8h , a9h , and aah ( i g nored for 32mb and 64mb banks ) ?as y mmetr y selection , as set b y bits [ 4:0 ] of syscfg d3h ( i g nored for 32mb and 64mb banks ) . the decodin g is shown in tables 4-20 , 4-21 , and 4-22. table 4-20 symmetrical dram address decoding memory address 1mb 2mb 4mb 8mb 16mb 32mb 64mb col row col row col row col row col row col row col row ma0 a2 a11 a2 a11 a2 a11 a2 a11 a2 a11 a2 a11 a2 a11 ma1 a3 a12 a3 a12 a3 a12 a3 a12 a3 a12 a3 a12 a3 a12 ma2 a4 a13 a4 a13 a4 a13 a4 a13 a4 a13 a4 a13 a4 a13 ma3 a5 a14 a5 a14 a5 a14 a5 a14 a5 a14 a5 a14 a5 a14 ma4 a6 a15 a6 a15 a6 a15 a6 a15 a6 a15 a6 a15 a6 a15 ma5 a7 a16 a7 a16 a7 a16 a7 a16 a7 a16 a7 a16 a7 a16 ma6 a8 a17 a8 a17 a8 a17 a8 a17 a8 a17 a8 a17 a8 a17 ma7 a9 a18 a9 a18 a9 a18 a9 a18 a9 a18 a9 a18 a9 a18 ma8 a10 a19 a10 a19 a10 a19 a10 a19 a10 a19 a10 a19 a10 a19 ma9 a21 a20 a21 a20 a21 a20 a21 a20 a21 a20 a21 a20 a21 a20 ma10 a23 a22 a23 a22 a23 a22 a23 a22 a23 a22 a23 a22 a23 a22 ma11 a25 a24 a25 a24 a25 a24 a25 a24 a25 a24 a25 a24 a25 a24 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 49 revision: 3.0 table 4-21 asymmetrical dram decoding, asymmetry syscfg d3h[4:0] = 0 table 4-22 asymmetrical dram decoding, asymmetry syscfg d3h[4:0] = 1 note: the shaded address lines in tables 4-21 and 4-22 should not be used for as y mmetrical dram decodin g, however , the y are still output durin g the memor y c y cle. memory address 1mb, 10x8 2mb, 11x8 4mb, 11x9 8mb, 12x9 16mb, 12x10 col row col row col row col row col row ma0 a2 a11 a2 a11 a2 a11 a2 a11 a2 a11 ma1 a3 a12 a3 a12 a3 a12 a3 a12 a3 a12 ma2 a4 a13 a4 a13 a4 a13 a4 a13 a4 a13 ma3 a5 a14 a5 a14 a5 a14 a5 a14 a5 a14 ma4 a6 a15 a6 a15 a6 a15 a6 a15 a6 a15 ma5 a7 a16 a7 a16 a7 a16 a7 a16 a7 a16 ma6 a8 a17 a8 a17 a8 a17 a8 a17 a8 a17 ma7 a9 a18 a9 a18 a9 a18 a9 a18 a9 a18 ma8 a10 a19 a10 a19 a10 a19 a10 a19 a10 a19 ma9 a21 a10 a21 a20 a21 a20 a21 a20 a21 a20 ma10 a23 a22 a23 a10 a23 a21 a23 a22 a23 a22 ma11 a25 a24 a25 a24 a25 a24 a25 a21 a25 a23 memory address 1mb, 11x7 2mb, 12x7 4mb, 12x8 8mb, 12x9 16mb, 12x10 col row col row col row col row col row ma0 a2 a11 a2 a11 a2 a11 a2 a11 a2 a11 ma1 a3 a12 a3 a12 a3 a12 a3 a12 a3 a12 ma2 a4 a13 a4 a13 a4 a13 a4 a13 a4 a13 ma3 a5 a14 a5 a14 a5 a14 a5 a14 a5 a14 ma4 a6 a15 a6 a15 a6 a15 a6 a15 a6 a15 ma5 a7 a16 a7 a16 a7 a16 a7 a16 a7 a16 ma6 a8 a17 a8 a17 a8 a17 a8 a17 a8 a17 ma7 a9 a18 a9 a18 a9 a18 a9 a18 a9 a18 ma8 a10 a19 a10 a19 a10 a19 a10 a19 a10 a19 ma9 a21 a10 a21 a20 a21 a20 a21 a20 a21 a20 ma10 a23 a9 a23 a10 a23 a21 a23 a22 a23 a22 ma11 a25 a24 a25 a9 a25 a10 a25 a21 a25 a23 82C465MV/mva/mvb opti ? pa g e 50 912-3000-016 revision: 3.0 4.4.2 dram bus drive capability b y settin g syscfg a1h [ 4 ] = 1 , the drive capab ilit y of certain ma bus si g nals and dram control si g nals is increased b y approximatel y 50% ( see table 4-23 ) . refer to the ac char- acteristics section of this document for determinin g whether this additional drive , at the rated capacitance and speed of the dram load , will eliminate the need for extra bus buffers on the memor y address lines. 4.4.3 setting up dram operation pro g rammin g the 82C465MV dram controller is a simple matter of: 1. settin g syscfg a0h [ 0 ] = 1 to enable simplified memor y pro g rammin g . 2. settin g syscfg 31h [ 5 ] accordin g to whether or not par- it y bit dram will be used ( not an available option if l2 cache is part of desi g n ) . 3. writin g the size and arran g ement of each bank to its cor- respondin g re g ister at syscfg a8h-aah. 4. settin g the as y mmetr y selection for that bank in the re g - ister at syscfg d3h if the dram is not s y mmetrical. 5. settin g the c y cle speed in at syscfg 35h. 6. selectin g the desired refresh rate throu g h syscfg 67h [ 6:5 ] . 7. enablin g dram refresh throu g h syscfg 57h [ 7 ] . the re g ister bits involved in settin g up dram operation are shown in table 4-24. table 4-23 heavy-duty memory bus drive capability feature 76543210 syscfg a1h feature control register 2 default = 00h heav y -dut y memor y bus drive: 0 = disable 1 = enable table 4-24 dram setup registers 76543210 syscfg a0h feature control register 1 default = 00h dram mappin g : 0 = disable 1 = enable syscfg 31h control register 2 default = 40h parit y check: 0 = enable 1 = disable syscfg a8h dram bank select register 1 default = 00h bank 1 t y pe: 0 = s y m 1 = as y m bank 1 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb bank 0 t y pe: 0 = s y m 1 = as y m bank 0 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 51 revision: 3.0 note: parit y checkin g ( syscfg 31h [ 5 ]) is alwa y s disabled if l2 cache option is enabled. syscfg a9h dram bank select register 2 default = 00h bank 3 t y pe: 0 = s y m 1 = as y m bank 3 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb bank 2 t y pe: 0 = s y m 1 = as y m bank 2 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb syscfg aah dram bank select register 3 default = 00h bank 4 t y pe: 0 = s y m 1 = as y m bank 4 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb syscfg d3h asym. dram select register default = 00h bank 4 as y m t y pe: 0 = 11x9 1 = 12x8 bank 3 as y m t y pe: 0 = 11x9 1 = 12x8 bank 2 as y m t y pe: 0 = 11x9 1 = 12x8 bank 1 as y m t y pe: 0 = 11x9 1 = 12x8 bank 0 as y m t y pe: 0 = 11x9 1 = 12x8 syscfg 35h dram control register 2 default = ffh standard dram read wait states: 00 = 3-2-2-2 01 = 4-3-3-3, 1 ws pa g e miss 10 = 4-3-3-3, 0 ws pa g e miss 11 = 5-4-4-4 dram write wait states: 00 = no wait states 01 = 1 wait state 10 = 1 wait state 11 = no wait states, ras# 1/2 clock earl y (mvb) syscfg 67h pmu control register 9 default = 00h refresh rate active or suspend mode: 00 = 15 s ( 30 s in suspend if syscfg a1h [ 6 ] = 0 ) 01 = 30 s 10 = 61 s 11 = 122 s syscfg 57h pmu control register 6 default = 00h refresh: 0 = disable 1 = enable table 4-24 dram setup registers (cont.) 76543210 82C465MV/mva/mvb opti ? pa g e 52 912-3000-016 revision: 3.0 4.4.3.1 faster memory cycles on the 82C465MV and 82C465MVa chipsets , 3-2-2-2 burst reads with zero wait state writes are possible onl y with 70ns or better dram. on the 82C465MVb part , ras# can be pro- g rammed to come one-half clock earl y on pa g e miss c y cles to g ive a wider timin g mar g in and permits the use of 80ns dram in this application. syscfg 35h [ 5:4 ] =11 , formerl y a reserved combination , select this c y cle as shown in table 4- 25. 4.4.3.2 dram mapping scheme enable settin g syscfg a0h [ 0 ] = 0 provides compatibilit y with bios code written for the 82c463mv chipset. the proper method for 82C465MV desi g ns is to set up the dram throu g h syscfg a8h , a9h , and d3h , then set syscfg a0h [ 0 ] = 1 before attemptin g to access dram. 4.4.3.3 dram control register 2i - syscfg 35h dram control re g ister 2 at syscfg 35h is not strictl y back- ward compatible with the 82c463mv chipset re g ister due to chan g es in the memor y controller timin g selections. however , the 82C465MV memor y controller will not fail if 82c463mv pro g rammin g is used; onl y slower operation will occur. refer to the 82c463mv data book for comparison of the syscfg 35h bit select functions. table 4-25 dram early ras# control 76543210 syscfg 35h dram control register 2 default = ffh dram write wait states: 00 = no wait states 01 = 1 wait state 10 = 1 wait state 11 = no wait states, ras# 1/2 clock earl y (mvb) syscfg 3fh misc. control register default = 00h minimum wait states for non-l2 cache s y stems: 0 = 1 ws 1 = 0 ws (mvb) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 53 revision: 3.0 4.4.4 edo dram support the 82C465MVb provides a dramatic performance improve- ment with the incorporation of edo dram support in its memor y controller. edo dram latches its output data while its input address chan g es in order to save an additional clock on most memor y read c y cles. the performance of a s y stem based on edo dram is nearl y as hi g h as a s y stem with l2 cache. edo dram re q uires special control of the dram we# pin to extend the data output duration. however , it re q uires no addi- tional pins. syscfg 3eh [ 4:0 ] enable edo dram support separatel y for each bank as indicated below. syscfg 3eh [ 7:6 ] select the read wait state timin g for edo banks. syscfg 35h [ 7:6 ] appl y onl y to standard dram. table 4-26 shows the above mentioned re g ister bits. 4.4.5 dram cycle speed the values t y picall y used for edo dram c y cle speed are shown in table 4-27. it is alwa y s recommended to perform a complete s y stem tim- in g anal y sis usin g the worst-case timin g parameters for the components chosen. the timin g recommended below assumes that fbclkin ( pin 144 ) clock timin g leads the pcu- clk timin g ( measured at the cpu ) . this is easil y achieved b y usin g the cpuclk dela y strap ( pin 78 ) noted in table 3-2. fbclkin leadin g cpuclk b y 0-2ns provides optimal timin g . table 4-26 edo dram selection table 4-27 suggested edo dram cycle speed settings 76543210 syscfg 3eh dram type select register default = 00h edo dram read wait states: 00 = 3-1-1-1 10 = 4-2-2-2 01 = 3-2-2-2 11 = reserved (mvb) bank 4 dram: 0 = standard 1 = edo (mvb) bank 3 dram: 0 = standard 1 = edo (mvb) bank 2 dram: 0 = standard 1 = edo (mvb) bank 1 dram: 0 = standard 1 = edo (mvb) bank 0 dram: 0 = standard 1 = edo (mvb) syscfg 35h dram control register 2 default = ffh standard dram read wait states: 00 = 3-2-2-2 01 = 4-3-3-3, 1 ws pa g e miss 10 = 4-3-3-3, 0 ws pa g e miss 11 = 5-4-4-4 1x cpu frequency dram speed read cycle timing write cycle timing 20mhz 80ns 3-2-2-2 0 wait state 25mhz 80ns 3-2-2-2 0 wait state 33mhz 70ns 3-2-2-2 0 wait state 33mhz 60ns 3-1-1-1 0 wait state 40mhz 70ns 3-2-2-2 1 wait state 82C465MV/mva/mvb opti ? pa g e 54 912-3000-016 revision: 3.0 4.4.6 system rom and shadow ram since accesses to local dram are much faster than those to rom , the 82C465MV provides shadow ram capabilit y . with this feature , code from slow devices can be copied to local dram for faster access. all accesses to the specified eprom space are redirected to the correspondin g dram location. the 82C465MV supports up to 256k b y tes of rom in the first 1mb of address space. the f000h se g ment is handled as one continuous 64k block , while the c000h , d000h and e000h se g ments each are divided into four 16k blocks that can be individuall y controlled. se g ments c000h , e000h and f000h can be shadowed , cached , or both; se g ment d000h can be shadowed but not cached. the procedure for confi g urin g shadow ram operatin g and loadin g the shadow ram is as follows. 1. select the blocks in the c00000-fffffh ran g e whose access should g enerate romcs#. the rom select re g isters shown in table 4-28 list the possible blocks. romcs# g eneration implies reads from the xd bus , so the xdir si g nal will direct the rom data onto the sd bus. if rom is on the isa bus ( such as for a video adapter ), the correspondin g romcs bit for that block should not be set. 2. globall y enable loadin g of the shadow dram. the write destination re g ister ( table 4-29 ) shows the control available: syscfg 36h [ 7 ] to enable writes to dram for all blocks c000-f000h , and syscfg 36h [ 6 ] for writes to dram in the c000h , d000h , and e000h blocks. syscfg 36h [ 7 ] must be set to 1 before syscfg 36h [ 6 ] can be set to 1. syscfg 38h [ 4:1 ], 37h [ 7:4 ], and 31h [ 3:0 ] are set accordin g to a common scheme , dependin g on the set- tin g s of syscfg 36h [ 7:6 ], as shown in table 4-30. table 4-28 rom select registers table 4-29 write destination registers 76543210 syscfg 38h block control register 1 default = 80h romcs for cc000: see table 4-30 romcs for c8000: see table 4-30 romcs for c4000: see table 4-30 romcs for c0000: see table 4-30 syscfg 37h d/e000 control register default = 0fh romcs for dc000: see table 4-30 romcs for d8000: see table 4-30 romcs for d4000: see table 4-30 romcs for d0000: see table 4-30 syscfg 31h control register 2 default = 40h romcs for ec000: see table 4-30 romcs for e8000: see table 4-30 romcs for e4000: see table 4-30 romcs for e0000: see table 4-30 76543210 syscfg 36h shadow ram control register 3 default = 10h f000 write select destination: 0 = dram 1 = rom don't care for f000 if syscfg 32h [ 7 ] = 0 c-d-e000 select destination: 0 = isa/rom 1 = dram see table 4-30 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 55 revision: 3.0 table 4-30 access control bit meanings for syscfg 38h[4:1], 37h[7:4], 31h[3:0] 3. cop y the information to be shadowed from rom to dram b y simpl y readin g from and then writin g back to the same location for each b y te of the block to be copied. the rom need not be located in the ph y sical bios rom; it can also be rom on the isa bus as selected in step 1. 4. a g ain usin g syscfg 36h [ 7:6 ], g loball y disable writes to the shadow dram. 5. select the rom blocks that have been shadowed in dram. the re g ister bits shown in table 4-31 are used to select the blocks that have been shadowed. enablin g f000h reads to come from dram ( syscfg 32h [ 7 ]) also automaticall y enables write protection for that dram block. table 4-31 shadow ram control bits note: f0000h-fffffh access control syscfg 32h[7] - this bit serves a dual purpose. settin g syscfg 32h [ 7 ] = 0 allows readin g from dram and write protect ( enable shadowin g) for the f000h block. settin g syscfg 32h [ 7 ] = 1 allows read- in g from romcs# , and writin g to romcs# ( if syscfg 36h [ 7 ] = 1 ) or to dram ( if syscfg 36h [ 7 ] = 0 ) . syscfg 36h[7:6] setting access control bit selection 00 0 = r/w from isa bus 1 = read from romcs#; writes disabled x1 0 = read from isa bus if not shadowed, write to dram 1 = read from romcs# if not shadowed, write to dram see syscfg 33h [ 7:0 ] and 36h [ 3:0 ] for shadowin g selection 10 0 = r/w from isa bus 1 = r/w from romcs# 76543210 syscfg 33h shadow ram control register 2 default = 00h ec000 read select rom/ram: 0 = rom 1 = shadow ram e8000 read select rom/ram: 0 = rom 1 = shadow ram e4000 read select rom/ram: 0 = rom 1 = shadow ram e0000 read select rom/ram: 0 = rom 1 = shadow ram dc000 read select rom/ram: 0 = rom 1 = shadow ram d8000 read select rom/ram: 0 = rom 1 = shadow ram d4000 read select rom/ram: 0 = rom 1 = shadow ram d0000 read select rom/ram: 0 = rom 1 = shadow ram syscfg 36h shadow ram control register 3 default = 10h cc000 read select rom/ram: 0 = rom 1 = shadow ram c8000 read select rom/ram: 0 = rom 1 = shadow ram c4000 read select rom/ram: 0 = rom 1 = shadow ram c0000 read select rom/ram: 0 = rom 1 = shadow ram syscfg 32h shadow ram control register 1 default = e4h f0000 access: 0 = dram 1 = rom 82C465MV/mva/mvb opti ? pa g e 56 912-3000-016 revision: 3.0 6. select the shadowed blocks that should be write pro- tected. the bits used to select the blocks to be write-pro- tected are shown in table 4-32. while f000h was automaticall y write-protected in the previous step , it can be unprotected ( for test purposes onl y) throu g h syscfg a1h [ 1 ] . the 82C465MV lo g ic provides special handlin g for write- protected dram areas ( rom shadowed in ram ) . nor- mall y, shadow ram selected as cacheable makes the ram cacheable in both l1 and l2 cache. however , selectin g shadow ram areas as write-protected makes them cacheable onl y in l2 cache ( if present ) . this provi- sion prevents loss of cache coherenc y between l1 cache and external ram ( if a pro g ram were to tr y to write to write-protected memor y that is cached in l1 cache , for example ) . 7. read accesses to bios and other rom code that has been shadowed will now come from dram. write accesses will be either blocked if write protection has been en g a g ed , or will be directed to the isa bus or to eprom otherwise. table 4-32 write protect registers 76543210 syscfg 32h shadow ram control register 1 default = e4h d000 block shadow control: 0 = writable 1 = protected e000 block shadow control: 0 = writable 1 = protected syscfg 36h shadow ram control register 3 default = 10h c000 write protect: 0 = writable 1 = protected syscfg a1h feature control register 2 default = 00h f000 shadow test: 0 = read or write 1 = read and write 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 57 revision: 3.0 4.5 cache control the 82C465MV mana g es several levels of cache: l1 write- throu g h , l1 writeback ( if supported b y the cpu ), and l2 writeback. 4.5.1 global enabling of cacheability the various levels of cache control must first be enabled indi- viduall y . then , settin g syscfg 35h [ 1 ] = 0 g loball y enables all individuall y enabled cache control features. this control bit is shown in table 4-33. 4.5.2 defining non cacheable blocks syscfg 38h-3bh are used to define two non-cacheable blocks. the startin g address for these blocks must have the same g ranularit y as the block size. for example , if a 512k- b y te non-cacheable block is selected , its startin g address is a multiple of 512k b y tes; conse q uentl y, onl y address bits of a [ 23:19 ] are si g nificant and a [ 18:16 ] are don't cares. table 4-34 shows the valid startin g address bits for all block sizes. the two non-cacheable blocks are defined throu g h the re g is- ters shown in table 4-35. table 4-33 global cache control enable table 4-34 size and valid start address bits of non-cacheable memory blocks note: v = valid bit; x = don't care table 4-35 non-cacheable block registers 76543210 syscfg 35h dram control register 2 default = ffh global cachin g control: 0 = enable 1 = disable syscfg 38h, and 3ah block size valid starting address bits 7 6 5 a24 a23 a22 a21 a20 a19 a18 a17 a16 0 0 0 64kb vvvvvvvvv 0 0 1 128kb vvvvvvvvx 0 1 0 256kb vvvvvvvxx 0 1 1 1mb vvvvvxxxx 1 x x disabled 76543210 syscfg 38h block control register 1 default = 80h non-cacheable block 1 ( ncb1 ) size: see table 4-34 ncb1 a24 syscfg 39h block control register 2 default = 00h - non-cacheable block 1 start address a [ 23:16 ] syscfg 3ah block control register 3 default = 80h non-cacheable block 2 ( ncb2 ) size: see table 4-34 ncb2 a24 syscfg 3bh block control register 4 default = 00h - non-cacheable block 2 start address a [ 23:16 ] 82C465MV/mva/mvb opti ? pa g e 58 912-3000-016 revision: 3.0 4.5.2.1 c000, e000, f000h block cache enable certain blocks in the option rom ran g e c0000-fffffh can be made cacheable. the cacheabilit y is effective onl y if the rom in that ran g e has been shadowed in dram. ? syscfg 35h [ 0 ] determines whether the 32kb block from c0000 to c7fffh will be cacheable. ? syscfg 35h [ 2 ] determines whether the 64kb block from f0000 to fffffh will be cacheable. ? syscfg 37h [ 3:0 ] determine the 16kb blocks from e0000 to effffh that w ill be cac heable. these enable bits are shown in table 4-36. table 4-36 c000, e000, f000h block cache enable 76543210 syscfg 35h dram control register 2 default = ffh f000 64kb block cacheable? 0 = yes 1 = no c000 32kb block cacheable? 0 = yes 1 = no syscfg 37h d/e000 control register default = 0fh ec00 16kb block cacheable? 0 = yes 1 = no e800 16kb block cacheable? 0 = yes 1 = no e400 16kb block cacheable? 0 = yes 1 = no e000 16kb block cacheable? 0 = yes 1 = no 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 59 revision: 3.0 4.5.2.2 cache control of c000-f000h the cache controller of the 82C465MVa chip can be used with either write-throu g h or writeback cpus , and with or with- out an external cache. the followin g subsections describe the operation of l2 cache in this re g ion. introduction cacheabilit y of c0000-fffffh starts out ver y simpl y . first of all , an y rom in these re g ions must be shadowed in dram; otherwise the area cannot be cached at either l1 or l2. sec- ond , syscfg 35h [ 1 ] must be set to 0 to g loball y enable cachin g . l1 cache control l1 cacheabilit y is interlinked with the 82c463mv-compatible memor y mappin g mode of the 82C465MVa chip. syscfg a0h [ 0 ] defaults to 0 , selectin g 82c463mv compatibilit y at reset. in this mode , cacheabilit y is available as follows. ? c0000h 32kb block: - cacheable in l1 when syscfg 35h [ 0 ] = 0. ? c8000h 32kb and d0000h 64kb blocks: - never cacheable. ? e0000 , e4000 , e8000 , and ec000h 16kb blocks: - cacheable in l1 when respective syscfg 37h [ 3:0 ] = 0. ? f0000 64kb block: - cacheable in l1 when syscfg 35h [ 2 ] = 0. this pro g rammin g scheme on the 82c463mv was not ver y secure , in that a shadowed re g ion of rom could be made cacheable in l1 y et write-protected in dram. in the case where an application pro g ram writes to the rom re g ion ( as windows? does , for example ), the content of l1 cache could be chan g ed without updatin g the memor y re g ion in dram ( which the 82c463mv would write-protect ) . this situation would become even more dan g erous in the case of a s y stem with l2 cache , since the dram , l2 cache , and l1 cache could all contain different values for the same memor y space. therefore , the 82c465 series chip introduced g reater protec- tion a g ainst this t y pe of pro g rammin g when not in 82c463mv-compatible mode. when syscfg a0h [ 0 ] is set to 1 , the 82C465MVa operates accordin g to the new memor y control scheme. this settin g automaticall y introduces an additional la y er of cacheabilit y control , re q uirin g that the re g ion also be declared read/writable before it becomes cacheable. ? c0000h 32kb block: - cacheable when syscfg 35h [ 0 ] = 0 and syscfg 36h [ 5 ] = 0 ( c000h writable ) . ? e0000 , e4000 , e8000 , and ec000h 16kb blocks: - cacheable when respective syscfg 37h [ 0:3 ] = 0 and syscfg 32h [ 3 ] = 0 ( e000h writable ) . ? f0000 64kb block: - cacheable when syscfg 35h [ 2 ] = 0 and syscfg a1h [ 1 ] = 1 ( f000h writable ) . this interlock ensures that the cpu cache contents will be coherent with the dram contents ( or at least the l2 cache contents ) at all times. l2 cache control l2 cacheabilit y is not affected b y the selection between 82c463mv-compatible memor y mappin g operation and 82C465MVa new memor y mappin g . l2 cacheabilit y control works essentiall y the same for all re g ions. ? c0000 , c4000 , c8000 , and cc000h 16kb blocks: - cacheable in l2 when respective syscfg d2h [ 3:0 ] =1 , alon g with syscfg 36h [ 5 ] = 0 or on an y read c y cle. ? d0000 , d4000 , d8000 , and dc000h 16kb blocks: - cacheable in l2 when respective syscfg d2h [ 7:4 ] = 1 , alon g with syscfg 32h [ 4 ] = 0 or on an y read c y cle. ? e0000 , e4000 , e8000 , and ec000h 16kb blocks: - cacheable in l2 when respective syscfg d1h [ 3:0 ] = 1 , alon g with syscfg 32h [ 3 ] = 0 or on an y read c y cle. ? f0000h 64kb block: - cacheable in l2 when syscfg 35h [ 2 ] = 0 , alon g with syscfg a1h [ 1 ] = 1 or on an y read c y cle. note that , as with 82C465MVa l1 cache control , writes to a re g ion are onl y cacheable if the re g ion is not write-protected. however , unlike l1 cache , reads are cacheable in l2 re g ard- less of the write-protect state of the re g ion. example here is a practical example of the cacheabilit y controls for a s y stem with l1 writeback and l2 cache. the s y stem is pro- g rammed for 82C465MV memor y mappin g so that the l1 cacheabilit y interlock is in place. 1. the setup code shadows rom code in the e0000- e7fffh re g ion , and sets syscfg 32h [ 3 ] = 1 to write- protect the re g ion. it also sets syscfg d1h [ 1:0 ] = 11 to make the re g ion cacheable in l2 , and syscfg 37h [ 0 ] = 0 to make the re g ion cacheable in l1. 2. application code reads the 1kb block startin g from e0000h. the block is write-protected , so it will not be cached in l1. however , it will be cached in l2. 3. the application modifies the 1kb block and writes it back to e0000h. since the block was never cached in l1 , there is no effect for the cpu. since the block is write- protected , the 82C465MVa prevents updatin g of both the l2 cache and the s y stem dram. so all memor y is still coherent. if the s y stem had been pro g rammed for 82c463mv-compati- ble memor y mappin g mode , the write-protect status of the block would not have mattered. when the cpu read the 82C465MV/mva/mvb opti ? pa g e 60 912-3000-016 revision: 3.0 block , it would have cached it in l1. when the cpu writes the block , it would have updated the block in l1 , but the l2 cache and the dram would have been write-protected. therefore , s y stem memor y would no lon g er be coherent. if the cpu accesses data in that re g ion a g ain , it will not be the same data that an external master would access ( even if the cpu performed a writeback c y cle ) . verifying l2 cache operation the followin g routine ma y prove useful in testin g whether l2 cache is bein g read and written properl y in an 82C465MV- based s y stem. the procedure can be run from debug com- mands if desired. an y errors indicate possible timin g prob- lems or ram failures. 1. pro g ram se g ments 0:0h throu g h 3000:0h to be non- cacheable. usin g non-cacheable block 2 , this would involve settin g syscfg 3ah [ 7:5 ] = 010 ( 256kb block ) and syscfg 3ah [ 0 ] + syscfg 3bh [ 7:0 ] = 0 ( start address 0:0 ) . in this wa y, the debu g pro g ram and all dos routines in low memor y will not involve cache. 2. enter debu g command: f 3000:0lffff 00 01 02 ... 0f to fill all of se g ment 3000h with a repeatin g pattern. 3. enter commands: m 4000:0lffff 8000:0 m 5000:0lffff 8000:0 m 6000:0lffff 8000:0 m 7000:0lffff 8000:0 to ensure that 9000:0 is not in l2 cache. 4. enter: m 3000:0lffff 9000:0 to cop y the pattern in se g ment 3000h to 9000h. l2 is unaffected. 5. enter: m 9000:0lffff 8000:0 to cop y the pattern into l2 as it is bein g read from se g - ment 9000h. 6. enter: 9000:0lffff 3000:0 to compare the data written to l2 to the ori g inal data pat- tern in dram. an y mismatches indicate a failure. from this point , there are two branches to the test. takin g branch ( a ) will test whether dram is corrupted b y new writes to l2 cache. takin g branch ( b ) will test whether dirt y data in l2 cache is g ettin g written back to dram properl y . to imple- ment the test completel y, it should g o from step 1 throu g h 9a the first time , and step 1 throu g h 10b the second time. branch (a) 7. enter: f 9000:0lffff 00 to fill l2 with data that is different from the ori g inal pat- tern. 8. disable l2 cache b y settin g syscfg d0h [ 5 ] = 0. 9. enter: c 9000:0lffff 3000:0 the comparison will take place a g ainst data in dram onl y, to determine whether it has been corrupted. an y mismatches indicate a failure. branch (b) 10. enter: f 9000:0lffff 20 21 22 ... 2f to fill se g ment 9000 with a new pattern. 11. enter: m 5000:0lffff 8000:0 to force se g ment 9000 to be written back to dram ( when the 5000 se g ment is read in , it has to occup y the spot where the se g ment 9000 data resides ) . 12. enter: f 3000:0lffff 20 21 22 ... 2f to fill se g ment 3000 with the same pattern written to se g - ment 9000. 13. enter: c 3000:0lffff 9000:0 to see whether the data forced out of l2 cache to se g - ment 9000 in dram is st ill the same pattern ori g inall y entered. an y mismatches indicate a failure. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 61 revision: 3.0 4.5.2.3 cache invalidation feature cachin g of write-protected dram in l1 cache is automati- call y prevented on the 82C465MVa part , because the chip can onl y write-protect the external l2 cache and the dram. a write to on-cpu cache would result in a loss of coherenc y between l1 cache and an y external memor y . on the 82C465MVb part , syscfg 3fh [ 2 ] provides the option of invalidatin g the cache line instead ( see table 4-37 ) . if syscfg 3fh [ 2 ] = 1 , and shadow ram is pro g rammed to be cacheable in l1 , a write to a shadow ram location results in g eneration of eads# and the invalidation of that cache line. this feature provides better performance. for example , fre q uentl y executed bios code shadowed at f000h can be cached in l1. table 4-37 write-protected dram cache control 4.5.3 l1 write-back cache support the 82C465MV incorporates support for cpus with a level- one ( on-chip ) writeback cache such as that found on the amd? 5x86 processor , the c y rix? 5x86 processor , and some intel? processors. 4.5.3.1 hardware considerations l1 writeback cache support re q uires two additional si g nals , hitm# and boff#. the 82C465MV bus controller mana g es l1 cache without re q uirin g dedicated pins b y usin g the follow- in g scheme. the lo g ic operates properl y onl y if the 82C465MV re g isters have been pro g rammed to reco g nize and g enerate l1 cache si g nals. ? hitm# is combined with the existin g d/c# input to the bus controller. since d/c# will alwa y s be hi g h durin g a bus snoop c y cle ( after eads# g oes active ), hitm# can be combined with d/c#. the d/c# input to the 82C465MV is a hitm# input for onl y one c y cle , on the second or third clock after it sees eads# active. ? boff# is g enerated externall y from the ahold output q ualified with the hitm# output of the 82C465MV lo g ic. when the lo g ic sets ahold active ( hi g h ) alon g with hitm# inactive ( hi g h ), boff# to the cpu must g o low to re q uest a restart of the current bus c y cle. because hitm# does not have a dedicated input , it is moni- tored onl y durin g a specific window after eads# occurs. the 82C465MV looks for hitm# to g o active on the second or third clock ed g es after eads# , accordin g to pro g rammin g ; this provision accounts for the dela y introduced b y the exter- nal g ate and ensures that all processors can meet the hitm# setup re q uirement of the cache support lo g ic. fi g ure 4-2 illustrates the t y pical circuit used to g enerate hitm# and boff#. figure 4-2 generation of hitm# and boff# a feature of the 82C465MVa and mvb chips allows the chips to g enerate two l1 writeback si g nals internall y to avoid usin g external g ates. ? boff# is possible on the tagcs# line if tagcs# is not used ( no l2 cache ) ? hitm# is possible on the flush# line if cache is flushed b y some other means ( b y software for example ) . however , these two si g nals must alwa y s be used to g ether. when boff# is g enerated internall y b y the 82c465 chip , its 76543210 syscfg 3fh misc. control register default = 00h invalidate l1 cache line on writes to wp dram: 0 = disable 1 = enable (mvb) cpu 82C465MV d/c# d/c# hitm# ahold boff# 82C465MV/mva/mvb opti ? pa g e 62 912-3000-016 revision: 3.0 source is the ahold output and the hitm# si g nal expected to be input on the flush# pin. if the flush# pin is not used to input hitm# , alwa y s use an external g ate to g enerate boff# from the combination of hitm# and ahold. 4.5.3.2 extra programmable pin options hitm# and boff# si g nal g eneration on the 82C465MVa part can be internal to avoid the re q uirement for two external g ates. note that these si g nals can be defined onl y if the new memor y control interface has been strap selected on pin 79 at reset. hitm# input option hitm# can be directl y input to the chip on the flush# pin. selectin g the hitm# option will allow better performance for cpus that cannot return hitm# fast enou g h for samplin g on the second clock after eads# when the external g ate solu- tion ( d/c#+hitm# ) is used. note that until the hitm# option is selected , pin 135 is an output and will drive a g ainst the hitm# si g nal. however , both si g nals will be drivin g hi g h in their normal state so no harm is done. note that the flush# output can be eliminated onl y when smbase is relocated to a000h/b000h. this relocation elimi- nates the need for g eneratin g flush# on entr y to smm , which is the onl y time the 82C465MV ever g enerates flush#. boff# output option pin 189 ( lclk/tagcs# ) is redefined as boff# after reset under the followin g conditions: 1. pin 79 ( dackmux0 ) sensed low at reset , indicatin g that the new 82C465MV memor y control interface must be enabled 2. pin 146 ( sa0 ) sensed hi g h at reset , indicatin g that the l2 cache interface is not used. the lclk function of pin 189 should never be needed on 82C465MV desi g ns , because it is the same 1x clock as fbclkout. also , the tagcs# function of pin 189 for l2 cache should never be needed on desi g ns usin g l1 write- back cache cpus. therefore , the pin chan g es function to accommodate the need for boff# on l1 writeback cpus. if desired , settin g syscfg d4h [ 0 ] = 1 will reassi g n pin 189 as lclk even thou g h conditions 1 and 2 above have been met. table 4-38 shows which re g isters to pro g ram for the above mentioned options. table 4-38 pin options 76543210 syscfg d6h pmu control register 10 default = 00h hitm# source: 0 = d/c# 1 = pin 135 (mva) syscfg d4h resistor control register 1 default = 00h redefine pin 189: 0 = boff# 1 = lclk (mva) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 63 revision: 3.0 4.5.3.3 programming the l1 cache option must first be preset throu g h settin g syscfg a0h [ 1 ] = 1. the hitm# sensin g is set accordin g to the cpu used and speed of operation throu g h syscfg d1h [ 7 ] . after cacheable ran g es have been established as described in the previous section , the cache operation is then enabled b y writin g syscfg 35h [ 1 ] = 1. table 4-39 shows these re g ister bits. l1 cache hitm# sensing syscfg d1h[7] - selects the c y cle durin g which the 82C465MV looks for hitm# after it sees eads# low. cpus that cannot reliabl y meet the setup time re q uirements for hitm# to be returned on the second clock after eads# should use the default third-clock settin g . ?0 = sample hitm# ( on d/c# input ) on second clock after samplin g eads# low ? 1 = sample hitm# on third clock after samplin g eads# low 4.5.3.4 burst write feature the 82C465MVa part provides the burst write feature for l1 writeback cpus. the feature is enabled onl y when the l1 writeback feature is enabled. on the 82C465MVb part , syscfg 3fh [ 4 ] allows the burst write feature to be enabled independentl y for non-l1 writeback cpus. re g ardless of the settin g of syscfg 3fh [ 4 ], burst writes are alwa y s enabled when the l1 writeback feature is selected. table 4-39 l1 writeback programming bits table 4-40 burst write control 76543210 syscfg a0h feature control register 1 default = 00h cpu cache operation select: 0 = standard 1 = l1 write- back syscfg d1h l2 cache control register 2 default = 41h l1 cache hitm# sensin g after eads#: 0 = 2nd clock 1 = 3rd clock syscfg 35h dram control register 2 default = ffh global cachin g control: 0 = enable 1 = disable 76543210 syscfg 3fh misc. control register default = 00h cpu burst write support: 0 = disable 1 = enable (mvb) 82C465MV/mva/mvb opti ? pa g e 64 912-3000-016 revision: 3.0 4.5.4 l2 cache support the 82C465MV incorporates support for an l2 ( external ) writeback cache. the l2 cache support is optional , and is en g a g ed when the 82C465MV initialization lo g ic sees sa0 low at hardware reset time. as soon as reset is complete , the lo g ic redefines a lar g e block of pins for l2 cache support. fi g - ure 4-3 illustrates the connection of the l2 cache to the chip. table 4-41 lists the no cache support interface versus the l2 cache support interface. figure 4-3 l2 cache connection - two bank configuration 16245 486 cpu opti isa bus 64mb or 256mb sram cd[31:16] sdenh# sdenl# sdir sd[15:0] cd[15:0] ca[31:2] ca[17:4] cd[31:0] cd[31:0] ccs[3:0]# 0123 eca3 ecawe# beoe# eca2 ocawe# booe# tag[7:0], drty tagcs#, tagwe# cd[31:24] cd[23:16] cd[15:8] cd[7:0] bank 1 cd[31:24] cd[23:16] cd[15:8] cd[7:0] bank 0 ta g 82C465MV 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 65 revision: 3.0 4.5.4.1 performance the l2 cache implementation is a full-performance scheme. because the 82C465MV provides all control si g nals and the ta g ram data connections directl y, there are no external buffer or g ate dela y s and no extra clocks re q uired for s y n- chronization. the inte g rated ccs0-3# select lines provide an additional feature. besides eliminatin g the need to externall y g ate w/r# with each of the be0-3# lines , these dedicated chip select lines g o active onl y when the cache is actuall y bein g accessed. conse q uentl y, the cache consumes less power when not activel y bein g accessed. 4.5.4.2 l2 cache operation details the inte g rated cache controller uses a direct-mapped , bank- interleaved scheme to dramaticall y boost the overall perfor- mance of the local memor y subs y stem b y cachin g writes as well as reads ( writeback mode ) . cache memor y can be con- fi g ured as one or two banks , and sizes of 64kb , 128kb , and 256kb are supported. the cache controller operates in non- pipeline mode , with a fixed 16-b y te line size ( optimized to match a 486 burst linefill ) in order to simplif y the motherboard desi g n without increasin g cost or de g radin g s y stem perfor- mance. for 486 s y stems , the secondar y cache operates independentl y and in addition to the internal cache of the cpu. cache bank interleave in order to support cache burst c y cles at elevated fre q uen- cies and still utilize conventional-speed srams , a bank-inter- leave cache access method is emplo y ed. the addresses are applied to the cache memor y one c y cle earlier , while cache output enable si g nals control even/odd bank selection and enable cache ram data to the cpu data bus. since the out- put enable time is about one-half of the address access time , the 82C465MV can achieve a hi g h performance cache burst mode without usin g more expensive hi g h-speed srams. the 82C465MV chip supports one or two cache banks. two cache banks are re q uired to interleave and optimall y realize the performance advanta g es of this cache scheme. a selec- tion of 128kb is a sin g le-bank cache , while 64kb and 256kb cache sizes are two-bank confi g urations. when usin g a two- bank confi g uration , the even and odd banks receive mostl y the same address lines; si g nals eca3/eca2 , ecawe#/ocawe# and beoe#/booe# are used to dictate the even or odd bank access. table 4-41 l2 cache support signal correspondence l2 cache support signal no cache support signal impact on system design beoe# ( o ) - cache output enable , even cd25 external buffers re q uired to move cd31:16 data down to sd15:0 booe# ( o ) - cache output enable , odd cd26 ecawe# ( o ) - cache write enable , even cd27 ocawe# ( o ) - cache write enable , odd cd28 tagwe# ( o ) - ta g ram write enable cd29 drty ( i/o ) - dirt y bit to/from ta g ram cd24 tag7:0 ( i/o ) - ta g ram data bus cd23:16 eca2 ( o ) - earl y ca2 cd30 eca3 ( o ) - earl y ca3 cd31 tagcs# ( o ) - ta g ram chip select lclk lclk no lon g er available sdir ( o ) - sd15:0 to cd31:16 buffer dir. xdir xdir must be derived externall y sdenh# ( o ) - sd15:8 to cd31:24 buffer en. kbdcs# none - combine with dwe# sdenl# ( o ) - sd7:0 to cd23:16 buffer en. rtcd# none - combine with romcs# ccs0# ( o - 3.3v ) - cache chip select 0 strp0 memor y parit y checkin g is no lon g er available ccs1# ( o - 3.3v ) - cache chip select 1 strp1 ccs2# ( o - 3.3v ) - cache chip select 2 strp2 ccs3# ( o - 3.3v ) - cache chip select 3 strp3 82C465MV/mva/mvb opti ? pa g e 66 912-3000-016 revision: 3.0 writeback cache the writeback cache scheme derives its superior perfor- mance b y optimizin g write c y cles. there is no performance penalt y in the cache write c y cle , since the cache controller does not need to wait for the much slower dram controller to finish its import before proceedin g to the next c y cle. tag ram a built-in ta g comparator improves s y stem performance while reducin g component count on the s y stem board. the com- parator internall y detects the cache hit/miss status b y com- parin g the hi g h-order address bits ( for the memor y c y cle in pro g ress ) with the stored ta g bits from previous cache entries ( see table 4-42 ) . when a match is detected , and the location is cacheable , a cache hit c y cle takes place. if the comparator does not match , or a non-cacheable location is accessed ( based on the internal non-cacheable re g ion re g isters ), the current c y cles is a cache miss. the ta g is invalidated automaticall y durin g memor y reads when the cache is disabled; each memor y read will write into the correspondin g ta g location a non-cacheable address ( such as a0000h or b0000h of the video memor y area ) . to flush the cache , simpl y disable the l2 cache and read a block of memor y e q ual to the size of the cache. the advanta g e of this invalidation scheme is that no valid bit is necessar y and expensive sram can be conserved. table 4-42 details cpu address bits that are stored as ta g s for the various cache sizes supported b y the cache controller. the table also marks the hi g h-order address bit in each con- fi g uration. this is the bit that can be eliminated in each con- fi g uration and replaced b y the dirt y bit if the desi g n must use an 8-bit wide ta g sram instead of a 9-bit wide device. table 4-43 illustrates the conse q uences of this choice for each con- fi g uration. table 4-42 correspondence between tag bits and cpu address lines note: * optional ta g bit table 4-43 maximum cacheable system dram for each cache configuration note: *not 64mb or 32mb because those addresses in the upper mb conflict with the value used to invalidate cache. dirty bit mechanism the dirt y bit is a mechanism for monitorin g data coherenc y between the external cache subs y stem and dram. each ta g entr y has a correspondin g dirt y bit to indicate whether the data in the represented cache line has been modified since it was loaded from s y stem memor y . this bit allows the cache controller to determine whether the data in memor y is stale and needs to be updated before a new memor y location is allowed to overwrite the currentl y indexed cache entr y . the writeback c y cle causes an entire cache line ( 16 b y tes ) to be written back to memor y, followed b y a line burst from the new memor y location into the cache and cpu. normall y, the per- formance advanta g e of completin g fast writes to the cache outwei g h the writeback read-miss penalties which are incurred while operatin g the writeback scheme. possible cache c y cles are detailed below: cache read-hit. the secondar y cache provides the data to the cpu directl y . the cache controller follows the cpu burst protocol to fill the internal cache line of the processor. cache read-miss (drty bit negated): import cycle. the cache controller does not need to update s y stem memor y with the current data from the cache , because that data has not been modified ( as shown b y the dirt y bit ne g ation ) . the cache controller asserts tagwe# to update the ta g rams with the new address , and asserts beoe#/booe# to update cache memor y with data from the new dram line. data is presented to the cpu and the secondar y cache concurrentl y ( followin g the 486 burst protocol ) . cache read-miss (drty bit asserted): castout cycle. the cache controller must update the s y stem memor y with data from the cache location that is g oin g to be overwritten. the cache controller writes the 16-b y te line from cache mem- or y into dram , then reads the new line from dram into the cache memor y and de-asserts the dirt y bit. the cache con- troller asserts tagwe# and beoe#/booe# durin g this line fill. this new data is presented to the cpu and to the second- ar y cache concurrentl y ( followin g the 486 burst protocol ) . tag bit 64kb cache 128kb cache 256kb cache 7 ca23* ca23 ca23 6 ca22 ca22 ca22 5 ca21 ca21 ca21 4 ca20 ca20 ca20 3 ca19 ca19 ca19 2 ca18 ca18 ca18 1 ca17 ca17 ca25* 0 ca16 ca24* ca24 tag/dirty sram width maximum dram possible 64kb cache 128kb cache 256kb cache 9-bit 16mb 32mb 63mb* 8-bit 8mb 16mb 31mb* 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 67 revision: 3.0 cache write-hit. because this is a writeback cache , the cache controller does not need to update the much slower dram memor y . instead , the controller updates the cache memor y and sets the drty bit. drty ma y alread y be set , but that does not affect this c y cle. the contents of the ta g ram remains unmodified. cache write-miss. the cache controller b y passes the cache entirel y and writes the data directl y into dram. the drty bit is unchan g ed. no import c y cle to the cache takes place. table 4-44 shows recommended data and tag sram speeds for relative cpu clock rates. 4.5.4.3 l2 cache arrangement the 82C465MVa part provides two new bits for g reater flexi- bilit y of l2 cache. ? syscfg d1h [ 4 ] selects sin g le-bank operation of l2 cache. the ori g inal 82C465MV part provided for sin g le- bank operation of 128kb cache onl y . this new feature allows 64kb and 256kb cache to operate in a sin g le bank mode. ? syscfg d1h [ 5 ] allows the use of a 7-bit ta g ram address in order to use an 8-bit wide ta g sram instead of a 9-bit wide sram. the ori g inal 82C465MV part allowed this arran g ement , but since there was no wa y to indicate to the chipset to make upper dram non cacheable , the 8-bit ta g ram selection would severel y limit the maximum pos- sible s y stem dram. these re g ister bits are shown in table 4-45. table 4-44 sram speed requirements notes: 1. dram and cache c y cles are at their minimum wait states. 2. 20ns sram with tdoe 10ns. 3. dram speed assumed to be 80ns minimum. table 4-45 l2 cache arrangement selection bit speed cache sram tag sram write wait states burst read timing (note 1) bank arrangement 16mhz 25ns 25ns 0 2-1-1-1 sin g le/double bank 20mhz 25ns 25ns 0 2-1-1-1 sin g le/double bank 25mhz 20ns 25ns 0 2-1-1-1 sin g le bank 25mhz 25ns 25ns 0 2-1-1-1 double bank 33mhz 20ns 15ns 0 3-2-2-2 sin g le bank cache 33mhz 20ns ( note 2 ) 15ns 0 2-1-1-1 double bank cache onl y 40mhz 20ns 15ns 1 3-2-2-2 sin g le/double bank 50mhz 20ns 15ns 1 3-2-2-2 sin g le/double bank 76543210 syscfg d1h l2 cache control register 2 default = 41h l2 ta g ram size: 0 = 8-bit 1 = 7-bit (mva) l2 cache arran g ement: 0 = two banks 1 = one bank (mva) 82C465MV/mva/mvb opti ? pa g e 68 912-3000-016 revision: 3.0 4.5.4.4 differences between l2 support and no cache support modes when the l2 cache feature is strap-selected , the followin g chan g es must be made to the s y stem desi g n. ?the cd [ 31:16 ] inputs to the 82C465MV controller lo g ic are redefined b y the l2 cache interface. cd [ 31:16 ] are used onl y for data exchan g es between the sd [ 15:0 ] bus and the cpu , and do not affect the cpu-to-memor y interface. enablin g l2 support re q uires the use of a word-wide , level- translatin g transceiver between cd [ 31:16 ] and sd [ 15:0 ] . whenever bus exchan g es take place between the isa bus and the local cpu bus , the 82C465MV isa controller directs data onto the correct b y te lanes as appropriate. ? the cache chip select lines ccs#0-3 become available. no parit y checkin g is available in the 82c465 series chip. ? rtcd# is multiplexed with romcs# on the old romcs# pin. the new pin is valid as rtcd# when aen is low , and as romcs# alwa y s. onl y rtcd# needs to be q ualified with aen , as romcs# to the rom is further q ualified b y memr# g oin g active. ? the old rtcd# pin becomes the low-b y te enable si g nal sdenl# to the cd-sd buffer. ? kbdcs# is multiplexed with dwe# on the old dwe# pin. the new pin is valid as kbdcs# when aen is low , and as dwe# alwa y s. onl y kbdcs# needs to be q ualified with aen , as dwe# to the dram is further q ualified b y one of the ras# lines g oin g active. ? the old kbdcs# pin becomes the hi g h-b y te enable si g nal sdenh# to the cd-sd buffer. ? the old xdir pin becomes the cd-sd buffer direction si g - nal sdir. s y stems that are desi g ned usin g the opti 82c602 chip do not need an xdir si g nal. for those desi g ns usin g discrete lo g ic for the xd bus , the xdir func- tion must be derived externall y usin g w/r# from the cpu to control xd bus buffer direction , and romcs#/rtcd# anded with dwe#/kbdcs# to enable the buffer. ? the old lclk pin becomes the tagcs# control line to ta g ram. the lclk function should not be needed in a new desi g n since the 82C465MV clock fbclkout runs at the proper speed for the vl bus ( alwa y s 1x ) . these functions are controlled separatel y from the l2 cache enable feature to allow s y stems to be desi g ned with all the l2 cache support lo g ic in place and operatin g, without actuall y havin g to install and enable the cache itself on ever y board. not until the enable l2 cache operation control bit is set in the feature control re g ister do the converted pins actuall y be g in to function for cache support. the strappin g option does , however , chan g e pin definitions so that the cd-sd buffer is used in all transactions involvin g cd [ 31:16 ] . table 4-46 illustrates the actual si g nal chan g es per pin. table 4-46 l2 cache support option (strap-selected) pin 82c463mv signal 82C465MV signal w/ l2 option strapped pin 82c463mv signal 82C465MV signal w/ l2 option strapped 149 xdir sdir 205 cd19 tag3 89 rtcd# sdenl# 204 cd20 tag4 104 kbdcs# sdenh# 203 cd21 tag5 90 romcs# romcs#+rtcd# 202 cd22 tag6 25 dwe# kbdcs#+dwe# 199 cd23 tag7 23 mp0 ccs0# 197 cd24 drty 13 mp1 ccs1# 196 cd25 beoe# 3 mp2 ccs2# 195 cd26 booe# 198 mp3 ccs3# 194 cd27 ecawe# 189 lclk tagcs# 193 cd28 ocawe# 2 cd16 tag0 192 cd29 tagwe# 207 cd17 tag1 191 cd30 eca2 206 cd18 tag2 190 cd31 eca3 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 69 revision: 3.0 4.5.4.5 hardware considerations the s y stem desi g ner should be aware of the followin g infor- mation when desi g nin g in l2 cache. dwe# is on the cpu/memor y interface and is therefore a 3.3v si g nal in a mixed-volta g e s y stem. since the dwe# pin is shared b y kbdcs# , kbdcs# is a 3.3v si g nal also. the 7432 g ate normall y used to decode kbdcs# usin g aen will have a 3.3v hi g h input. if a 5.0v g ate is used , the 3.3v inactive input at low-power suspend time could cause a current drain. also , the sense of sdir is as follows: lo g ic hi g h indicates an a-to-b exchan g e which is from cd [ 31:16 ] to sd [ 15:0 ] ; lo g ic low indicates a b-to-a exchan g e which is from sd [ 15:0 ] to cd [ 31:16 ] . s y stem desi g ners must be careful to orient the 'a' and 'b' sides of the buffer properl y . l2 cache is often placed on its own separate power plane so that it can be powered down when the s y stem suspends. syscfg d0h [ 6 ] is provided as explained below to select whether the cache control si g nals will be tristated or j ust driven inactive ( hi g h ) durin g suspend. 4.5.4.6 programming support for l2 cache is enabled b y strappin g sa0 low as described in table 3-2 , strap option summar y, on pa g e6. an y s y stem desi g ned for l2 cache should enable this sup- port , whether the cache is actuall y installed or not. the size of the cache , the wait states , and the cacheable areas are pro g rammed in l2 cache control re g isters 1 , 2 , and 3. then , the cache is actuall y enabled for operation b y writin g syscfg d0h [ 5 ] = 1. note: when l2 cache is enabled , the 82C465MV part re q uires the dram controller to run no faster than 4-3-3-3 dram read c y cles. table 4-47 l2 cache registers 76543210 syscfg d0h l2 cache control register 1 default = c0h l2 cache ccs0-3# deassert: 0 = stop g rant and sus- pend 1 = also between accesses l2 cache con- trols suspend state: 0 = tristate 1 = driven l2 cache en g a g e: 0 = disable 1 = enable cache size: 00 = 64kb 01 = 128kb 10 = 256kb 11 = reserved l2 cache write wait state: 0 = 1 ws 1 = no ws l2 cache read burst wait state control: 0 = x-1-1-1 1 = x-2-2-2 l2 cache first read wait state control: 0 = 3-x-x-x 1 = 2-x-x-x syscfg d1h l2 cache control register 2 default = 41h l2 cache arran g ement: 0 = two banks 1 = one bank (mva) ec000- effffh l2 cacheable? 0 = no 1 = yes e8000- ebfffh l2 cacheable? 0 = no 1 = yes e4000-e7fffh l2 cacheable? 0 = no 1 = yes e0000-e3fffh l2 cacheable? 0 = no 1 = yes syscfg d2h l2 cache control register 3 default = 00h dc000- dffffh l2 cacheable? 0 = no 1 = yes d8000- dbfffh l2 cacheable? 0 = no 1 = yes d4000- d7fffh l2 cacheable? 0 = no 1 = yes d0000- d3fffh l2 cacheable? 0 = no 1 = yes cc000- cffffh l2 cacheable? 0 = no 1 = yes c8000- cbfffh l2 cacheable? 0 = no 1 = yes c4000- c7fffh l2 cacheable? 0 = no 1 = yes c0000- c3fffh l2 cacheable? 0 = no 1 = yes 82C465MV/mva/mvb opti ? pa g e 70 912-3000-016 revision: 3.0 l2 chip select control syscfg d0h[7] - selects when the ccs0-3# and tagcs# si g nals should g o inactive. some cache ram ma y not be read y for access in time if its chip enable is turned off between c y cles. settin g syscfg d0h [ 7 ] = 0 lets ccs0-3# and tagcs# g o inactive onl y durin g stop grant c y cles and durin g suspend mode. settin g syscfg d0h [ 7 ] = 1 lets ccs0-3# and tagcs# g o inactive between cache accesses as well as durin g stop grant and suspend mode. l2 chip select state during suspend syscfg d0h[6] - allows cache to be flushed and turned off durin g suspend mode if desired to save power. software must perform the flush. l2 cache engage syscfg d0h[5] - enables l2 writeback cache operation if chip was strapped for l2 cache confi g ura- tion. otherwise , the bit settin g has no effect. this bit would remain set to 0 on a s y stem that was predisposed to accept cache but on which no cache was presentl y installed. l2 cache read burst wait state control syscfg d0h[1] - when syscfg d0h [ 1 ] = 0 , read hit burst c y cles run with no wait states ( x-1-1-1 ) . when syscfg d0h [ 1 ] = 1 , read hit burst c y cles run with one wait state ( x-2-2-2 ) . l2 cache first read wait state control syscfg d0h[0] - when syscfg d0h [ 0 ] = 0 , the first read hit c y cle runs with no wait states ( 2-x-x-x ) . when syscfg d0h [ 0 ] = 1 , the first read hit c y cle runs with one wait state ( 3-x-x-x ) . 4.5.4.7 timing control register the superior performance of edo dram re q uires timin g that is ti g hter than for standard dram. this timin g becomes especiall y critical durin g an l2 cache read miss c y cle , because the dram read and l2 cache write occurs in the same clock c y cle and from the same clock ed g e. therefore , the 82C465MVb part provides syscfg 3ch [ 2:0 ] . these bits control the number of g ate dela y s inserted to dela y the cache ecawe# , ocawe# , and tagwe# si g nals so that the l2 cache write occurs after edo dram read data is read y . the re q uired settin g for these bits depends on s y stem la y out. a value of 100b* , 4 g ate dela y s , is t y pical. table 4-48 cache timing control 76543210 syscfg 3ch timing control register default = 00h l2 cache we# dela y (mvb) : 000 = no dela y 100 = 4 g ate dela y s* 001 = 1 g ate dela y 101 = 5 g ate dela y s 010 = 2 g ate dela y s 110 = 6 g ate dela y s 011 = 3 g ate dela y s 111 = 7 g ate dela y s 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 71 revision: 3.0 4.6 peripheral interface logic the peripheral interface lo g ic of the 82C465MV chip includes isa bus control lo g ic , the 82c206-t y pe ipc , the inte g rated local bus ide controller , and the compact isa ( cisa ) inter- face. 4.6.1 isa bus logic the 82C465MV handles all the t y pical aspects of isa bus operation. 8- or 16-bit transactions can take place on the isa bus , dependin g on the state of the io16# and m16# lines dur- in g the transaction. all isa bus commands g enerated b y the cpu will be passed first to the vl bus. if no local device responds b y activatin g ldev# , the 82C465MV bus controller runs the c y cle on the isa bus. even i/o accesses that are destined for internal devices such as the dma controller and interrupt controller will be presented on the isa bus. it is therefore important that no external device attempt to respond to these c y cles as well. bus contention and invalid data could result. note that write accesses to internal confi g uration re g isters at 022h and 024h are also available outside the chip for an y external lo g ic that needs to record these transactions. read accesses to these re g isters are available onl y on the cpu interface. 4.6.1.1 hardware considerations the desi g n of the isa subs y stem is heavil y dependent on the load and the tar g et power consumption. for example , a 3.3v isa subs y stem is ideal in terms of power consumption char- acteristics , y et not all isa bus peripherals can operate at 3.3v. therefore , the desi g ner ma y need to separatel y buffer 3.3v and 5.0v buses and implement a control isolation mech- anism. in addition the desi g ner must consider the xd bus , which also can be either 3.3v or 5.0v , and determine whether this separate local peripherals bus is necessar y as described below. xd bus buffer control the lo g ic provides an xdir si g nal to control the movement of 8-bit isa bus data to and from the sd [ 15:0 ] bus , alwa y s on the lower b y te. when the xdir si g nal is not available , as when the l2 cache interface is selected , the buffer direction can be derived from memr# and ior# , and the buffer enable from romcs# , rtcd# , and kbdcs#. note that a separate xd bus is not alwa y s needed in a desi g n. if there are not a lar g e number of devices on the sd bus , the xd bus peripherals can simpl y be placed directl y on the sd bus. the onl y absolute re q uirement for a separate xd bus is for desi g ns in which sd and xd run at different volt- a g es and the xd bus buffer acts also as a level translator. sd bus buffer control the internal bus controller lo g ic automaticall y splits word or double-word writes from the cpu to multiple 8-bit isa bus c y cles. if the respondin g device asserts m16# or io16# , the bus controller will transfer 16 bits at a time. conversel y, cpu memor y reads , which can be 32-bits wide , will automaticall y be assembled b y the 82C465MV bus con- version lo g ic either b y te-b y -b y te or word-b y -word , dependin g on whether m16# is asserted b y the peripheral. the b y tes or words are moved individuall y from the sd bus to the appro- priate lanes on the cd bus as indicated b y the cpu be [ 3:0 ] # lines until the complete data word is read y . the 82C465MV lo g ic then finall y asserts rdy# to transfer the 8- , 16- , or 32- bit data back to the cpu. sd-to-cd bus buffer controller when the l2 cache interface is implemented , the cd [ 31:16 ] si g nal interface is converted to various ta g data and cache control si g nals. since the cd [ 31:16 ] inputs are alwa y s moved down to the sd [ 15:0 ] bus an y wa y, this operation is readil y achieved usin g an external 16-bit transceiver. in most cases the transceiver will also be a level-translator , since the cd bus is g enerall y 3.3v and the sd bus is 5.0v. a 74fct164245 level translator device or a 74lvt16245 5.0v- tolerant device are often used for this purpose as shown in fi g ure 4-3 on pa g e 64. for an y data exchan g e that re q uires a direct b y te or word movement from cd [ 31:16 ] to sd [ 15:0 ], the bus controller sets the direction on sdir to point to the sd bus , sets its internal sd bus buffer to input ( so it can capture the data bein g written to the isa bus in case it needs to act on the data ), and then enables sdenh# or sdenl# as appropriate. for direct movement from sd [ 15:0 ] to cd [ 31:16 ], the process is similar but the sdir direction chan g es. once a g ain , the bus controller captures the data on its internal sd [ 15:0 ] lines in case it needs to act on the data. for an y operation that involves a b y te-swap , the bus control- ler must direct the cd-sd buffer output to its internal sd [ 15:0 ] input. it then latches this data , performs the re q uired b y te swap , disables the sdenh# and sdenl# lines to the cd-sd buffer , and finall y drives the correctl y swapped data to the isa bus. these operations take place at cpu clock speeds , not isa bus speeds; therefore , the impact on operational speed is ne g li g ible. 82C465MV/mva/mvb opti ? pa g e 72 912-3000-016 revision: 3.0 master# control the internal lo g ic can reco g nize an y active drq and an active hlda from the cpu as an indication that an isa bus peripheral device has bus ownership. it can further determine that the device is a bus master , as opposed to a dma slave , b y lookin g at the state of aen. therefore , the 82C465MV can determine whether the current isa bus c y cle is a master c y cle without havin g to observe the master# input pin. the ri# pin was formerl y shared with the master# input on the 82c463 chipset and can continue to act as a master# input if syscfg 30h [ 5 ] is written to '0' ( see table 4-49 ) . however , this function need not be supported and should not be implemented in new desi g ns. master# from the isa bus should be used onl y to control the direction of an y ca-to-sa bus buffers in use. 4.6.1.2 isa write cycle inhibition the c y cle enable bits listed in table 4-50 default to enabled to allow write accesses to the isa bus or eprom to be g en- erated normall y . in those situations where roms are present , the write c y cles can be blocked. table 4-49 pin 186 function select table 4-50 cycle enable bits 76543210 syscfg 30h control register 1 default = 40h pin 186 function: 0 = master# 1 = ri 76543210 syscfg 32h shadow ram control register 1 default = e4h allow d000 writes: 0 = disable 1 = enable allow e000 writes: 0 = disable 1 = enable syscfg 36h shadow ram control register 3 default = 10h allow c000 writes: 0 = disable 1 = enable 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 73 revision: 3.0 4.6.1.3 isa bus clock options the isa bus can run at exactl y 8.0mhz on the 82C465MV if an appropriate external clock is provided. this feature re q uires a new input pin , atclkin. if this feature is enabled , atclkin will replace the pio2 si g nal presentl y found on pin 172 of the 82c463mv. atclkin is simpl y an alternative clock source. it can be divided in the same wa y as the fbclkin source. an 8.0mhz clock will most likel y be derived b y dividin g a 16mhz atclkin b y 2 , or a 24mhz atclkin b y 3. the atclkin input for this function must be enabled first as explained previousl y in section 4.3.2 "system clock genera- tion" . the clock can then be selected b y writin g syscfg 43h [ 3 ] = 1 , and usin g syscfg 43h [ 2:0 ] to choose the divisor ( see table 4-52 ) . bit 3 defaults to 0 on power-up. note: the 82C465MV can run from either a 1x clock or a 2x clock ( refer to the section 3.3 "strap-selected interface options" for details ) . to remain compatible in both modes , the at bus clock selections are based on the fbclkin ( feedback ) clock times 2. this scheme effectivel y maintains the same rate as would have been selected throu g h 82c463mv pro g ram- min g . 4.6.1.4 isa bus refresh control the 82C465MVb part allows refresh on the isa bus to be completel y eliminated. since ver y few isa bus devices actu- all y make use of the refresh c y cle , this bandwidth can be recovered to improve s y stem performance. settin g syscfg 32h [ 2 ] = 0 disables hidden refresh on the isa bus and g ener- ation of addresses for refresh as well , but does not in an y wa y affect local s y stem dram refresh. table 4-51 isa bus refresh control table 4-52 atclkin programming register bits 76543210 syscfg 32h shadow ram control register 1 default = e4h hidden refresh on isa bus: 0 = enable 1 = disable* (mvb) * enable when usin g edo dram. 76543210 syscfg 43h pmu control register 4 default = 00h atclk g enerator source: 0 = fbclkin 1 = atclkin w/syscfg a0h [ 4 ] = 1 atclk rate selections: 000 = /8 100 = 7.2 mhz 001 = /6 101 = /2 010 = /4 110 = /1 ( /2 if syscfg43h [ 3 ] = 0 ) 011 = /3 111 = stop syscfg a0h feature control register 1 default = 00h pin 172 function: 0 = pio2 ( or cpuspd ) 1 = atclkin 82C465MV/mva/mvb opti ? pa g e 74 912-3000-016 revision: 3.0 4.6.1.5 programming the isa bus re q uires a certain amount of pro g rammin g in order to preset and optimize its operation for the peripheral devices chosen. table 4-53 shows the related re g ister pro- g rammin g bits and the followin g explains their functions. turbo vga forces zero wait state operation from memor y accesses at addresses a0000h to b0000h , as if nows# were alwa y s active. at wait state control adds one extra wait state to each isa bus c y cle , useful for slower devices. master byte swap control enables isa bus b y te swappin g for bus masters. while some isa bus masters are capable of monitorin g the iocs16# and memcs16# isa bus si g nals to determine where to drive data , others depend on the s y stem to do the b y te swap for them. this bit allows either t y pe of bus master to be accommodated. ale control during bus conversion allows selection of a sin g le ale on the first c y cle or an ale on the subse q uent command c y cle as well when word accesses are split into two separate b y te accesses. most all newer peripheral devices re q uire two separate ales. internal i/o address decode size selection allows address- in g to wrap around ever y 400h ports or to end after 100h. s y stem desi g ns with peripheral devices at aliases of the 0- ffh ran g e ( for example , an i/o device addressed at 420h ) should use 16-bit decodin g to prevent the internal peripheral devices from respondin g at aliased addresses and conflictin g with the external devices. table 4-53 peripheral device programming register bits 76543210 syscfg 30h control register 1 default = 40h turbo vga ( nows# ) : 0 = disable 1 = enable at wait states: 0 = none 1 = one syscfg 31h control register 2 default = 40h master b y te swap: 0 = disable 1 = enable syscfg 32h shadow ram control register 1 default = e4h ales in bus conversion: 0 = multiple 1 = sin g le syscfg a0h feature control register 1 default = 00h internal i/o address decodin g : 0 = 10-bit 1 = 16-bit pin 172 function: 0 = pio2 ( or cpuspd ) 1 = atclkin 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 75 revision: 3.0 4.6.1.6 isa bus address buffer enable signal the 82C465MVa interface provides the sabufen# si g nal output as a strap-selected option on pin 172. pin 172 is nor- mall y used for the cpuspd output indicator , the atclkin bus clock input function , or as g eneral purpose i/o pin pio2. as pio2 , pin 172 defaults to input mode at power-up time. when the new function is pro g rammed , pin 172 becomes the sabufen# output. sabufen# is normall y hi g h , and drives low on an y isa bus access ( includin g dma , refresh , etc. ) . this si g nal is enabled earl y in all c y cles so that the ca [ 23:2 ] bits can be driven onto the sa [ 23:2 ] bus in time for decode b y isa peripheral devices. the 82C465MVa enables a weak internal pull-down resistor on pin 172 after reset to enable an y connected buffer. once syscfg 57h ( where input or output is selected for each pio pin ) is written with an y value , the internal pull-down resistor is disabled. 4.6.1.7 docking station attachment feature the hot attachment of a notebook computer to a dockin g station throu g h the isa bus re q uires the abilit y to stop an y isa c y cle in pro g ress and tristate the bus. the 82C465MVa part implements this feature throu g h an unused interrupt line on the multiplexed epmmux input. on the 82C465MV part , inputs c0-c3 to epmmux are defined as drq2 , rsvd , epmi3 , and epmi4. the rsvd line is alwa y s shown as pulled low in the current schematics. on the 82C465MVa part , the c1 input is redefined from rsvd to athold. brin g in g athold hi g h causes the 82C465MVa lo g ic to stop the cpu operation after the current bus c y cle is complete. since athold is reco g nized throu g h a multiplexer , there is a maximum latenc y of 280ns from assertion of athold to rec- o g nition b y the lo g ic. in addition , there is the time re q uired for the s y stem to complete its current c y cle , which could take on the order of microseconds for certain isa bus c y cles. finall y, the isa bus si g nals are all tristated and will remain tristated as lon g as athold is hi g h. brin g in g athold low a g ain restarts the s y stem. this feature is alwa y s enabled. table 4-54 pio2 and sabufen# program bits 76543210 syscfg 57h pmu control register 6 default = 00h pio2 direction: 0 = input 1 = output syscfg 79h pmu control register 11 default = 00h pin 172 function: 0 = pio2 or cpuspd 1 = buffer enable pin sabufen# (mva) 82C465MV/mva/mvb opti ? pa g e 76 912-3000-016 revision: 3.0 4.6.2 programmed hardware reset the 82C465MVa part allows g eneration of hardware reset si g nal cpurst b y writin g a re g ister bit. this function is use- ful for restorin g the re g isters to their default condition in cer- tain situations. for example , if a flash bios has been repro g rammed , the s y stem must be re-initialized and booted properl y . usin g this bit ma y eliminate the need for some hard- ware reset lo g ic. 4.6.3 integrated peripheral controller the inte g rated peripheral controller ( ipc ) includes two 8237 dma controllers , two 8259 interrupt controllers , one 8254 timer/counter and one 74612 memor y mapper. it is re g ister- compatible with the 82c206 chip. for information on the desi g n architecture of this unit , refer to the separate document on the 82c206 ipc. this document is available on re q uest from opti. 4.6.3.1 multiplexor hardware considerations the 82C465MV uses an external multiplexin g scheme to read in man y of the irq , drq , and external pmi inputs. the scheme uses the kbclk and kbclk2 outputs to to gg le a 74153-t y pe multiplexer throu g h four distinct samplin g phases. while the s y stem is active , kbclk and kbclk2 are g enerated from the osc14 input and sample each multi- plexer input once ever y 280ns. durin g suspend , if osc14 is not present the 32khz si g nal is used to g enerate kbclk and kbclk2. therefore , the inputs are sampled onl y once ever y 120 s in this case. samplin g occurs between multiplexer input switchin g . for example , when in active mode and runnin g off osc14 , kbclk/kbclk2 switch the multiplexer input ever y 70ns. the chipset samples the state of its input 35ns after the multi- plexer has switched. therefore , no g litchin g occurs on sam- plin g . the samplin g points are shown in fi g ure 4-5 , where the smpl14 si g nal is a dela y ed internal version of the osc14 input si g nal. external peripheral devices that g enerate irqs or external pmis must therefore g enerate a pulse of sufficient duration to be seen b y the samplin g lo g ic. the opti 82c602 notebook companion chip incorporates a latchin g mechanism to ensure that irq inputs that pulse low will be held low for at least one complete kbclk/kbclk2 c y cle ( 280ns or 120 s ) . 4.6.3.2 dma hardware considerations dma address after high memory access the 82C465MVb part incorporates automatic pulldown resis- tors on the cpu address lines. the chip manufacturin g pro- cess allows for resistor values between 40k and 60k ohm to be implemented internall y . most of the time , either the cpu or the chipset drives the address lines. the resistors are intended to prevent floatin g of the address lines when no one is drivin g, such as durin g bus hold periods. durin g dma c y cles , the dma controller within the 82C465MVb chipset drives the address on the cpu address bus; the cpu is in hold acknowled g e state at this time and does not drive an address. however , the dma controller does not drive address lines above ca23. ( even if it did , the dma controller still would not be able to control lines ca26- ca30 since the y do not connect to the 82C465MVb part. ) if the last cpu access j ust prior to bein g put in hold was to an address in hi g h memor y, one in which an y of ca24-ca31 was hi g h , the value on these address lines ma y remain hi g h when eads# is g enerated. if the bus capacitance is hi g h enou g h , weak internal or external pulldown resistors will not be sufficient to restore the address line value to 0 before the dma c y cle takes place. in this situation , the cpu will see the wron g address when eads# is asserted , and will not invali- date the proper line in l1 cache. address lines ca24 to ca31 should be pulled down exter- nall y with 2k ohm resistors. this stron g pulldown value ensures that the line will return to lo g ic '0' before eads is asserted. aen and 16-bit dma the 82c465 series drops aen earlier than the isa specifica- tion allows durin g 16-bit dma transfers. the aen si g nal should remain hi g h at least for the duration of the isa com- mand lines ( iord#/iowr# , mrd#/mwr# ) durin g dma. but aen will drop low mid-wa y throu g h the command , possibl y allowin g an i/o device to decode the transfer as a standard input/output command. the 82c465 chip itself can decode this c y cle and han g the s y stem under certain circumstances. generall y this failure mode is evident onl y when writeback cpu operation is enabled. there are several possible workarounds to this issue. ? if there is no possibilit y of 16-bit dma occurrin g, no workaround is re q uired. ? if no local isa devices will misinterpret the dma transfer as an i/o access , it is sufficient to simpl y set re g ister 43h [ 2:0 ] =000 to enable s y nchronous atclk operation. the internal lo g ic of the 82c465 chips will not misinterpret the dma access as an i/o access when in s y nchronous mode. ? if full isa support is expected , the fix shown in the fi g ure below must be implemented usin g two 7432 g ates and a 7408 g ate. note that if isa masters are not supported , the 7408 g ate is not re q uired. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 77 revision: 3.0 figure 4-4 correcting aen for 16-bit dma table 4-55 programmed hardware reset bit figure 4-5 multiplexed input sampling points 4.6.3.3 ipc configuration programming the sole confi g uration re g ister of the ipc , separate from those of the 82C465MV , is accessed b y first writin g the re g is- ter index of interest to i/o port 022h; the selected re g ister information then becomes available for readin g or writin g at i/o port 023h as opposed to port 024h used b y the 82C465MV confi g uration re g isters ( syscfg ) . table 4-56 shows the ipc confi g uration bits. 4.6.3.4 interrupt controller register programming the ipc provides two peripheral interrupt controllers that are re g ister compatible with the 8259 part. the re g isters of this lo g ic module are listed below. these re g isters are accessed directl y throu g h the i/o subs y stem ( no index/data method is used ) . initialization command words the initialization command words ( icws ) are shown first and must alwa y s be written in se q uence startin g with icw1. two i/o port g roups are listed. the first g roup refers to intc1 , the interrupt controller for irqs 0-7; the second refers to intc2 , the interrupt controller for irqs 8-15. refer to table 4-57 and table 4-58. 76543210 syscfg adh feature control register 3 default = 00h generate cpurst immediatel y ? 0 = no 1 = yes (mva) 82c465 dackmux1 dackmux0 465aen mstr# from isa bus aen to isa bus 280ns smpl14 kbclk kbclk2 465mv samples multiplexed input four times for ever y kbclk2 c y cle 82C465MV/mva/mvb opti ? pa g e 78 912-3000-016 revision: 3.0 table 4-56 ipc configuration bits table 4-57 intc1 initialization command words 76543210 index 01h ipc configuration register ipc re g ister access wait states ( atclks ) : 00 = 1 wait states 01 = 2 wait states 10 = 3 wait states 11 = 4 wait states ( default ) 16-bit dma wait states ( 1 ) : 00 = 1 wait state ( default ) 01 = 2 wait states 10 = 3 wait states 11 = 4 wait states 8-bit dma wait states ( 1 ) : 00 = 1 wait state ( default ) 01 = 2 wait states 10 = 3 wait states 11 = 4 wait states dela y dma memr# one clock from s y s- tem memr#? 0 = yes ( at- compatible - default ) 1 = no dma clock select: 0 = atclk/2, ( default ) 1= atclk ( 1 ) note that iochrdy can also be asserted b y dma devices to add wait states to dma c y cles. 76543210 port 020h icw1 (wo) don't care alwa y s = 1 tri gg er mode: 0 = ed g e 1 = level don't care cascade mode select? 0 = yes ( alwa y s ) 1 = no don't care port 021h icw2 (wo) v [ 7:3 ] - upper bits of interrupt vector. for at compatibilit y , write 08h. not used - lower bits of interrupt vector are g ener- ated b y interrupt controller. port 021h icw3 (wo) s [ 7:0 ] - slave mode controller connections. for at compatibilit y , write 04h ( irq2 ) . port 021h icw4 (wo) don't care enable multiple interrupts? 0 = no 1 = yes don't care enable auto end-of-inter- rupt command? 0 = no 1 = yes don't care table 4-58 intc2 initialization command words 76543210 port 0a0h icw1 (wo) don't care alwa y s = 1 tri gg er mode: 0 = ed g e 1 = level don't care cascade mode select? 0 = yes ( alwa y s ) 1 = no don't care port 0a1h icw2 (wo) v [ 7:3 ] - upper bits of interrupt vector. for at compatibilit y , write 70h. not used - lower bits of interrupt vector are g ener- ated b y interrupt controller. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 79 revision: 3.0 enable multiple interrupts can be enabled to allow intc2 to full y nest interrupts without bein g blocked b y intc1. cor- rect handlin g of this mode re q uires the cpu to issue a non specific eoi command to zero when exitin g an interrupt ser- vice routine. if the feature is disabled , no command need be issued. automatic end of interrupt can be enabled to allow the interrupt controller to g enerate a non specific eoi command on the trailin g ed g e of the second interrupt acknowled g e c y cle from the cpu. the feature allows the interrupt currentl y in service to be cleared automaticall y on exit from the service routine. this function should not be used with full y nested interrupts except b y intc1. port 0a1h icw3 (wo) don't care id [ 2: ] - slave mode address. for at compatibilit y , write 02h ( irq2 ) . port 0a1h icw4 (wo) don't care enable multiple interrupts? 0 = no 1 = yes don't care enable auto end-of-inter- rupt command? 0 = no 1 = yes don't care table 4-58 intc2 initialization command words (cont.) 76543210 82C465MV/mva/mvb opti ? pa g e 80 912-3000-016 revision: 3.0 operational command words the operational command words are used to pro g ram the interrupt controller durin g the course of normal operation. two i/o port addresses are listed for each re g ister. the first address refers to intc1 , the interrupt controller for irqs 0-7; the second refers to intc2 , the interrupt controller for irqs 8-15. table 4-59 shows the re g isters. table 4-59 intc1 and intc2 operational command words 76543210 port 021h, 0a1h ocw1 mask register irq7/15: 0 = enable 1 = mask irq6/14: 0 = enable 1 = mask irq5/13: 0 = enable 1 = mask irq4/12: 0 = enable 1 = mask irq3/11: 0 = enable 1 = mask irq2/10: 0 = enable 1 = mask irq1/9: 0 = enable 1 = mask irq0/8: 0 = enable 1 = mask port 020h, 0a0h ocw2 command re g ister ( wo ) 000 = disable auto-rotate, auto eoi mode 100 = enable auto-rotate, auto eoi mode 001 = generate nonspecific eoi 011 = generate specific eoi 101 = rotate on nonspecific eoi 111 = rotate on specific eoi 110 = set priorit y 010 = no operation alwa y s = 0 for ocw2 alwa y s = 0 for ocw2 l [ 2:0 ] - interrupt level acted on b y set priorit y and rotate of specific eoi port 020h, 0a0h ocw3 command register (wo) alwa y s = 0 allow bit 5 chan g es? 0 = no 1 = yes special mask mode: 0 = disable 1 = enable alwa y s = 0 for ocw3 alwa y s = 1 for ocw3 polled mode: 0 = disable (g enerate interrupt ) 1 = enable ( poll 020/ 0a0h for interrupt ) allow bit 0 chan g es? 0 = no 1 = yes in-service access: 0 = 020/0a0h reads return irr 1 = return isr port 020h, 0a0h interrupt request register ocw3[0] = 0 (ro) irq7/15 pendin g ? 0 = no 1 = yes irq6/14 pendin g ? 0 = no 1 = yes irq5/13 pendin g ? 0 = no 1 = yes irq4/12 pend- in g ? 0 = no 1 = yes irq3/11 pendin g ? 0 = no 1 = yes irq2/10 pendin g ? 0 = no 1 = yes irq1/9 pendin g ? 0 = no 1 = yes irq0/8 pendin g ? 0 = no 1 = yes port 020h, 0a0h in-service register ocw3[0] = 1 (ro) irq7/15 in-service? 0 = no 1 = yes irq6/14 in-service? 0 = no 1 = yes irq5/13 in-service? 0 = no 1 = yes irq4/12 in-service? 0 = no 1 = yes irq3/11 in-service? 0 = no 1 = yes irq2/10 in-service? 0 = no 1 = yes irq1/9 in-service? 0 = no 1 = yes irq0/8 in-service? 0 = no 1 = yes port 020h, 0a0h polled mode register ocw3[2] = 1 (ro) interrupt pendin g ? 0 = no 1 = yes not used irq [ 2:0 ] - number of hi g hest priorit y interrupt that is pendin g 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 81 revision: 3.0 interrupt controller shadow registers values written to the interrupt controller are not alwa y s directl y readable in the at architecture. however , the 82C465MV shadows these values as the y are written so that the y can be read back later throu g h the confi g uration re g is- ters. table 4-60 lists the correspondence of shadow indexes to the write-onl y re g isters in the interrupt controllers. 4.6.3.5 dma controller programming registers the ipc provides two direct memor y access controllers ( dmac1 and dmac2 ) and their associated memor y mappers that are re g ister compatible with at-t y pe s y stems. the re g is- ters of this lo g ic module are listed below. these re g isters are accessed directl y throu g h the i/o subs y stem ( no index/data method is used ) . each dmac has four dma channels. chan- nels 0-3 are in dmac1 , channels 4-7 in dmac2. table 4-61 and table 4-62 list the re g ister locations while table 4-63 and table 4-64 list the re g ister bit formats. followin g the re g ister bit formats tables is table 4-65 which lists the dma commands. table 4-60 interrupt controller shadow register index values table 4-61 dma address and count registers table 4-62 dma control and status register register intc1 index intc2 index icw1 80h 88h icw2 81h 89h icw3 82h 8ah icw4 83h 8bh ocw2 85h 8dh ocw3 86h 8eh name dma channel 0 addr. dma channel 1 addr. dma channel 2 addr. dma channel 3 addr. dma channel 4 addr. dma channel 5 addr. dma channel 6 addr. dma channel 7 addr. memor y address re g ister 000h r/w 002h r/w 004h r/w 006h r/w 0c0h r/w 0c4h r/w 0c8h r/w 0cch r/w count re g ister 001h r/w 003h r/w 005h r/w 007h r/w 0c2h r/w 0c6h r/w 0cah r/w 0ceh r/w pa g e address re g ister 087h r/w 083h r/w 081h r/w 082h r/w 08fh r/w 08bh r/w 089h r/w 08ah r/w command function command port address for dma channels 0-3 command port address for dma channels 5-7 mode re g ister sets the function t y pe for each channel. group can be read back - see reset mode re g ister readback counter com- mand read/write 00bh read/write 0d6h status re g ister returns channel re q uest and terminal count information read 008h read 0d0h command re g ister sets the dmac confi g uration write 008h , read 00ah write 0d0h , read 0d4h re q uest re g ister makes a software dma re q uest read/write 009h read/write 0d2h mask re g ister enables or masks dma transfers on selected channels read/write 00fh read/write 0deh temporar y re g ister not used in at-compatible desi g n read 00dh read 0dah 82C465MV/mva/mvb opti ? pa g e 82 912-3000-016 revision: 3.0 table 4-63 dmac1 control and status bits 76543210 port 008h dmac1 status register ch. 3 re q uest pendin g ? 0 = no 1 = yes ch. 2 re q uest pendin g ? 0 = no 1 = yes ch. 1 re q uest pendin g ? 0 = no 1 = yes ch. 0 re q uest pendin g ? 0 = no 1 = yes ch. 3 reached terminal count? 0 = no 1 = yes ch. 2 reached terminal count? 0 = no 1 = yes ch. 1 reached terminal count? 0 = no 1 = yes ch. 0 reached terminal count? 0 = no 1 = yes port 00bh dmac1 mode register mode select: 00 = demand 01 = sin g le 10 = block 11 = cascade address count: 0 = increment 1 = decrement auto-initialize: 0 = disable 1 = enable transfer select: 00 = verif y 01 = memor y write 10 = memor y read 11 = reserved channel select: 00 = channel 0 01 = channel 1 10 = channel 2 11 = channel 3 port 009h dmac1, dma request register reserved. write as 0. re q uest: 0 = clear 1 = set channel select: 00 = channel 0 01 = channel 1 10 = channel 2 11 = channel 3 port 008h dmac1 command register dack active sense: 0 = low 1 = hi g h drq active sense: 0 = hi g h 1 = low extended write: 0 = disable 1 = enable rotatin g priorit y : 0 = disable 1 = enable compressed timin g : 0 = disable 1 = enable dmac operation: 0 = enable 1 = disable channel 0 address hold: 0 = disable 1 = enable memor y -to- memor y : 0 = disable 1 = enable port 00fh dmac1 mask register reserved. write as 0. channel 3: 0 = unmasked 1 = masked channel 2: 0 = unmasked 1 = masked channel 1: 0 = unmasked 1 = masked channel 0: 0 = unmasked 1 = masked 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 83 revision: 3.0 table 4-64 dmac2 control and status bits table 4-65 dma commands 76543210 port 0d0h dmac2 status register ch. 7 re q uest pendin g ? 0 = no 1 = yes ch. 6 re q uest pendin g ? 0 = no 1 = yes ch. 5 re q uest pendin g ? 0 = no 1 = yes ch. 4 re q uest pendin g ? 0 = no 1 = yes ch. 7 reached terminal count? 0 = no 1 = yes ch. 6 reached terminal count? 0 = no 1 = yes ch. 5 reached terminal count? 0 = no 1 = yes ch. 4 reached terminal count? 0 = no 1 = yes port 0d6h dmac2 mode register mode select: 00 = demand 01 = sin g le 10 = block 11 = cascade address count: 0 = increment 1 = decrement auto-initialize: 0 = disable 1 = enable transfer select: 00 = verif y 01 = memor y write 10 = memor y read 11 = reserved channel select: 00 = channel 4 01 = channel 5 10 = channel 6 11 = channel 7 port 0d2h dmac2, dma request register reserved. write as 0. re q uest: 0 = clear 1 = set channel select: 00 = channel 4 01 = channel 5 10 = channel 6 11 = channel 7 port 0d0h dmac2 command register dack active sense: 0 = low 1 = hi g h drq active sense: 0 = hi g h 1 = low extended write: 0 = disable 1 = enable rotatin g priorit y : 0 = disable 1 = enable compressed timin g : 0 = disable 1 = enable dmac operation: 0 = enable 1 = disable channel 0 address hold: 0 = disable 1 = enable memor y -to- memor y : 0 = disable 1 = enable port 0deh dmac2 mask register reserved. write as 0. channel 7: 0 = unmasked 1 = masked channel 6: 0 = unmasked 1 = masked channel 5: 0 = unmasked 1 = masked channel 4: 0 = unmasked 1 = masked command function command port address for dma channels 0-3 command port address for dma channels 5-7 set sin g le mask bits re g ister sets or clears individual mask re g ister bits without havin g to do a read/modif y /write of the mask re g ister write 00ah: bits [ 1:0 ] select the channel, bit [ 2 ] selects the new mask bit value write 0d4h: bits [ 1:0 ] select the channel, bit [ 2 ] selects the new mask bit value clear mask unmasks all dma channels at once write an y value to 00eh write an y value to 0dch reset mode re g is- ter readback counter resets the mode re g ister readback function to start at re g ister 0. the next four mode re g is- ter reads then return channels 0, 1, 2, and 3 for that dmac read 00eh ( then read 00bh four times to g et the mode re g ister values ) read 0dch ( then read 0d6h four times to g et the mode re g ister values ) master clear clears all values, masks all channels, j ust like a hardware reset write an y value to 00dh write an y value to 0dah clear b y te pointer flip-flop resets the b y te pointer flip-flop so that the next b y te access to a word-wide dma re g ister is to the low b y te write an y value to 00ch write an y value to 0d8h set b y te pointer flip- flop sets the b y te pointer flip-flop so that the next b y te access to a word-wide dma re g ister is to the hi g h b y te read 00ch read 0d8h 82C465MV/mva/mvb opti ? pa g e 84 912-3000-016 revision: 3.0 4.6.3.6 determining dma status before suspend the 82C465MVa is the first chip in the opti 82c46x famil y to allow dma transfer status to be determined before sus- pendin g operation. in this wa y, complete s y stem context can be saved to disk and restored at an y time , even to the point of bein g able to reload and restart dma operations such as dma-driven audio applications. stopping dma activity in smm on receivin g a suspend re q uest , smm code ma y want to stop dma and determine the current state of all dma periph- eral devices. this would be difficult to do b y maskin g the channels , since the mask re g ister must be read first to deter- mine the channels that are unmasked and then masked. b y time this read/modif y /write c y cle is completed , transfer com- pletion on a channel ma y have caused one of the unmasked channels to be masked. the 82C465MVa lo g ic provides a dma smi enable , syscfg d6h [ 6 ], that traps to smm on an y dma re q uest without actuall y servicin g the re q uest. this same bit can be set from within smm to stop an y dma in pro g ress. the dma will not restart until syscfg ddh [ 4 ] is written to 1 to clear the event. if another dma transfer then occurs , it too will be blocked if syscfg d6h [ 6 ] is still set to 1. once dma is stopped , smm code can read the in-pro g ress bits to q uickl y determine the state of transfers on each chan- nel. these bits are set on the first drq after a channel is unmasked , and cleared b y a tc on that channel. once known , this information allows the code to decide how to properl y save and then restore the state of each channel as described in the followin g sections. table 4-66 dma progress bits 76543210 syscfg d6h pmu control register 10 default = 00h dma trap pmi#28 smi: 0 = disable 1 = enable (mva) dmac1 b y te pointer flip-flop ( ro ) : 0 = cleared 1 = set (mva) syscfg 84h dma in-progress register (ro) default = xxh channel 7 dma in pro g ress: 0 = no 1 = possibl y channel 6 dma in pro g ress: 0 = no 1 = possibl y channel 5 dma in pro g ress: 0 = no 1 = possibl y dmac2 b y te pointer flip- flop ( ro ) . 0 = cleared 1 = set (mva) channel 3 dma in pro g ress: 0 = no 1 = possibl y channel 2 dma in pro g ress: 0 = no 1 = possibl y channel 1 dma in pro g ress: 0 = no 1 = possibl y channel 0 dma in pro g ress: 0 = no 1 = possibl y syscfg ddh pmu smi source register 4 default = 00h pmi#28, dma: 0 = clear 1 = active (mva) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 85 revision: 3.0 4.6.3.7 dma register read back provisions the 82C465MVa part provides the means of readin g those dma re g ister settin g s that are normall y not accessible in order to restore the state after powerin g down the chip. saving count and address registers on the 82C465MVa part , onl y the current address and count values can be read back. the base values are not shadowed and cannot be read directl y . however , this does not prohibit savin g and restorin g base values. usin g the count re g isters as an example , when the smm suspend code starts to exe- cute the possible states of the dma transfer are: not yet started. the current count and the base count will be identical. completed on an auto-initialized channel. the base count will be restored to the current count and the two will be identi- cal. completed on a non auto-initialized channel. the base count is meanin g less and can be restored to the current count ( which will be ffffh after dma completion ) . in mid-transfer on an auto-initialized channel. the current count and base count will be different. smm code must per- form the followin g steps. 1. read back the current count. 2. set the channel to block verif y mode and make a soft- ware re q uest to start the transfer. 3. read back the current count , which now will reflect the base count instead ( at the end of the transfer the current count will be auto-initialized to the base count ) . in mid-transfer on a non auto-initialized channel. the base count is meanin g less. onl y the current count needs to be read back. for all these cases , the re g ister values can be read back directl y from the dma controller re g isters to which the base values were ori g inall y written. saving mode and mask register contents the ipc in the 82C465MVa part provides the means of read- in g back the mode and mask re g isters. perform the followin g steps , involvin g s y stem i/o ports ( not 82C465MVa confi g ura- tion re g isters ) . 1. read i/o port 00eh to reset the mode re g ister readback counter for dmac 1 2. do four successive reads from i/o port 00bh to retrieve mode re g isters 0-3 3. read i/o port 00fh to return channel 0-3 mask bits in bits 0-3 4. read i/o port 0dch to reset the mode re g ister readback counter for dmac 2 5. do four successive reads from i/o port 0d6h to retrieve mode re g isters 4-7 6. read i/o port 0deh to return channel 4-7 mask bits in bits 0-3. determining programming and transfer progress aside from the re g isters alread y listed , the 82C465MVa lo g ic shadows the b y te pointer flip-flop and provides special in- pro g ress indicators for each channel. usin g this information alon g with the readable dmac re g ister information , smm suspend code can save the state of the dmac as follows. 1. read and save the dma mode and mask re g isters from the pmu. 2. read the in-pro g ress bits to determine whether dma could be takin g place on an y channel. these bits are set on the first drq after a channel is unmasked , and cleared b y a tc on that channel. 3. read the pmu b y te pointer flip-flop settin g for each dmac. 4. clear the b y te pointer flip-flops b y writin g the appropriate dmac re g isters. 5. read and save all current count and current address val- ues from the dmac. the 82C465MVa part can now be powered down. restoring registers on resume on resumin g operation , the dmac re g ister values can be restored as follows. 1. restore the dmac mode and mask re g ister values. 2. restore the dmac count and address values. 3. if either of the saved pmu b y te pointer flip-flop settin g s indicates that a flip-flop was set , perform one read from an appropriate dmac count or address re g ister to set the flip-flop to its ori g inal state. 82C465MV/mva/mvb opti ? pa g e 86 912-3000-016 revision: 3.0 4.6.3.8 ldev# sense control when the 82C465MV chip runs dma to a local-bus device ( usuall y the video controller ), the chip g enerates ads# instead of the cpu. durin g a dma write c y cle ( i/o read , local- bus write ), the chip waits to sample ldev# and ads# low at the same time before it enables its buffer to drive sd bus data back to the local bus. if the local bus is heavil y loaded , the data ma y not be read y in time for the local-bus device to latch it. the 82C465MVa part provides a pro g ram bit to select a dif- ferent samplin g method in the case of dma to the local bus ( see table 4-67 ) . when syscfg d6h [ 3 ] = 0 , samplin g is as with the 82C465MV. when syscfg d6h [ 3 ] = 1 , the buffer enable control depends onl y on ldev# and not on ads#. effectivel y, the samplin g window occurs one clock earlier. local-bus devices that decode ldev# from address and sta- tus alone should have no problem meetin g the earl y sample re q uirement of this settin g . 4.6.3.9 type f dma support improved dma transfer performance is available on a chan- nel-b y -channel basis for those devices capable of shorter isa command pulses. normall y the 82C465MVb dma c y cle width is six at clocks for the read command and four at clocks for the write command. enablin g t y pe f dma for a channel chan g es this timin g as follows. ? for isa dma devices: read command ( ior# or memr# ) is two at clocks , write command ( iow# or memw# ) is one at clock. ? for cisa dma devices: cmd# is three at clocks; memr# or memw# is also three at clocks. t y pe f dma is controlled throu g h the eisa re g ister scheme. onl y the bits shown are supported ( see table 4-68 ) . table 4-67 ldev# sampling for dma to local bus table 4-68 type f dma control 76543210 syscfg d6h pmu control register 10 default = 00h local bus dma ldev# samplin g : 0 = normal 1 = sample one clock sooner (mva) 76543210 port 40bh (0-3) (mvb) eisa dma extended mode register not imple- mented. not imple- mented. c y cle timin g : 00 = isa-compatible 01 = isa-compatible 10 = isa-compatible 11 = t y pe f not imple- mented. not imple- mented. dma channel: 00 = channel 0 01 = channel 1 10 = channel 2 11 = channel 3 port 4d6h (4-7) (mvb) eisa dma extended mode register not imple- mented. not imple- mented. c y cle timin g : 00 = isa-compatible 01 = isa-compatible 10 = isa-compatible 11 = t y pe f not imple- mented. not imple- mented. dma channel: 00 = reserved 01 = channel 5 10 = channel 6 11 = channel 7 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 87 revision: 3.0 4.6.3.10 timer programming registers the ipc provides an 8254-t y pe timer with three channels that is re g ister compatible with at-t y pe s y stems. the re g isters of this lo g ic module are listed below. these re g isters are accessed directl y throu g h the i/o subs y stem ( no index/data method is used ) . table 4-69 lists the re g ister locations while table 4-70 g ives the re g ister bit formats. table 4-69 timer control and status registers table 4-70 timer control bits name function port address for timer channel 0 channel 1 channel 2 counter re g isters access used to write and read the word-wide count. writes alwa y s pro g ram the base value. reads return either the instantaneous count value or the latched count value. 040h 041h 042h counter mode command selects the operational mode for each timer counter. write 043h counter latch command latches the count from the selected re g ister for readin g at the associ- ated counter re g ister access port. write 043h then read 040h, 041h, and/or 042h readback command selects whether count or status, or both, will be latched for subse q uent readin g at the associated counter re g ister access port. if both are selected, status is returned first. this command can latch information from more than one counter at a time. write 043h then read 040h, 041h, and/or 042h 76543210 port 043h counter mode command (wo) counter select: 00 = counter 0 01 = counter 1 10 = counter 2 11 = readback command ( see below ) counter access: 00 = counter latch command ( see below ) 01 = r/w lsb onl y 10 = r/w msb onl y 11 = r/w lsb followed b y msb mode select: 000 = m0 ) interrupt on terminal count 001 = m1 ) hardware retri g . one-shot x10 = m2 ) rate g enerator x11 = m3 ) s q uare wave g enerator 100 = m4 ) software-tri gg ered strobe 101 = m5 ) hardware-tri gg ered strobe count mode select: 0 = 16-bit binar y 1 = 4-decade bcd port 043h counter latch command (wo) counter select: 00 = counter 0 01 = counter 1 10 = counter 2 11 = ille g al counter latch command = 00 don't care port 043h readback command (wo) readback command = 11 latch count? 0 = yes 1 = no latch status? 0 = yes 1 = no counter 2 select? 0 = yes 1 = no counter 1 select? 0 = yes 1 = no counter 0 select? 0 = yes 1 = no reserved: write as 0. port 043h status byte (ro) out si g nal status null count - counter con- tents valid? 0 = yes 1 = no ( bein g updated ) return bits [ 5:0 ] written in counter mode command ( see above ) 82C465MV/mva/mvb opti ? pa g e 88 912-3000-016 revision: 3.0 shadow registers to support timer values written to the timer are not alwa y s directl y readable in the at architecture. however , the 82C465MV shadows these values as the y are written so that the y can be read back later throu g h the confi g uration re g isters ( see table 4-71 ) . the val- ues from syscfg 90h to 96h are valid onl y when a counter mode command b y te for the counter has been written to the timer re g ister at i/o port 043h. settin g port 043h [ 5:4 ] = 11 starts the se q uence. 4.6.3.11 writing/reading i/o port 070h the at architecture does not allow the readback of the nmi enable bit settin g s and the rtc index value written at i/o port 070h. however , the 82C465MV lo g ic makes the nmi enable bit settin g, alon g with the last rtc index value written to i/o port 070h , available for readin g in its shadow re g ister set. table 4-72 shows the bit format for this re g ister. rtc index shadow register this shadow re g ister is read as a normal 82C465MV confi g u- ration re g ister: write 98h to i/o port 022h followed immedi- atel y b y an i/o read at i/o port 024h. table 4-73 shows the bit formats for this re g ister. table 4-71 timer shadow registers table 4-72 rtc index register - i/o port 070h table 4-73 rtc index shadow register 76543210 syscfg 90h timer channel 0 count low byte: a[7:0] default = xxh syscfg 91h timer channel 0 count high byte: a[15:8] default = xxh syscfg 92h timer channel 1 count low byte: a[7:0] default = xxh syscfg 93h timer channel 1 count high byte: a[15:8] default = xxh syscfg 94h timer channel 2 count low byte: a[7:0] default = xxh syscfg 95h timer channel 2 count high byte: a[15:8] default = xxh syscfg 96h write counter high/low byte latch default = xxh unused unused channel 2 read lsb to gg le bit channel 1 read lsb to gg le bit channel 0 read lsb to gg le bit channel 2 write lsb to gg le bit channel 1 write lsb to gg le bit channel 0 write lsb to gg le bit 76543210 port 070h rtc index register (wo) nmi enable: 0 = disable 1 = enable rtc/cmos ram index 76543210 syscfg 98h rtc index shadow register (ro) default = 00h nmi enable settin g - cmos ram index last written 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 89 revision: 3.0 4.6.3.12 additional floppy support the 82C465MVa part allows flopp y re g ister writes to be shadowed for easier mana g ement of power-down operations. re g ister writes to primar y fdc port addresses 3f2h and 3f7h , and to secondar y fdc port addresses 372h and 377h , are alwa y s copied to the 82C465MVa shadow re g isters. in addition , the 82C465MVa lo g ic provides a new re g ister bit to select whether additional fdc port accesses should be monitored b y dsk_access. on the ori g inal 82C465MV part , onl y port 3f5h is monitored. if the new bit is set to enable additional monitorin g, dsk_access will monitor i/o reads and writes to all primar y and secondar y fdc port addresses. note that this feature can be used in con j unction with the new i/o port address re g isters at syscfg d6h and d7h to determine which re g ister access caused the trap. table 4-74 shows the formats for the above mentioned bits. 4.6.3.13 irq8 polarity the reco g nition of the irq8 interrupt can be inverted throu g h syscfg 50h [ 5 ] ( see table 4-75 ) . in the normal at architec- ture , irq8 is active low and driven b y an open-collector out- put of the rtc a g ainst a pull-up resistor. if the 82C465MV chip is used in con j unction with the 82c602 notebook com- panion chip , irq8 polarit y should be set to active hi g h. table 4-74 floppy shadow and control registers table 4-75 pmu control register - syscfg 50h 76543210 syscfg 9bh 3f2h+3f7h shadow register default = 00h shadows 3f2h [ 7 ] mode select bit (mva) shadows 3f7h [ 1 ] disk t y pe bit 1 (mva) shadows 3f2h [ 5 ] drive 2 motor bit (mva) shadows 3f2h [ 4 ] drive 1 motor bit (mva) shadows 3f2h [ 3 ] dma enable bit (mva) shadows 3f2h [ 2 ] soft reset bit (mva) shadows 3f7h [ 0 ] disk t y pe bit 0 (mva) shadows 3f2h [ 0 ] drive select bit (mva) syscfg bch 372h+377h shadow register default = 00h shadows 372h [ 7 ] mode select bit (mva) shadows 377h [ 1 ] disk t y pe bit 1 (mva) shadows 372h [ 5 ] drive 2 motor bit (mva) shadows 372h [ 4 ] drive 1 motor bit (mva) shadows 372h [ 3 ] dma enable bit (mva) shadows 372h [ 2 ] soft reset bit (mva) shadows 377h [ 0 ] disk t y pe bit 0 (mva) shadows 372h [ 0 ] drive select bit (mva) syscfg d6h pmu control register 10 default = 00h dsk_access: 0 = 3f5h onl y 1 = all fdc ports ( 3f2,4,5,7h and 372,4,5,7h ) (mva) access trap bit a9 ( ro ) (mva) access trap bit a8 ( ro ) (mva) syscfg d7h access port address register default = 00h access trap address bits a [ 7:0 ] : - these bits, alon g with a [ 9:8 ] in bits d6h [ 1:0 ] , provide the 10-bit i/o address of the port access that caused the smi trap. syscfg d6h [ 2 ] indicates whether an i/o read or i/o write access was trapped. (mva) 76543210 syscfg 50h pmu control register 5 default = 00h irq8 polarit y : 0 = active low 1 = active hi g h 82C465MV/mva/mvb opti ? pa g e 90 912-3000-016 revision: 3.0 4.6.4 integrated local-bus enhanced ide interface enhanced ide support throu g h the local bus is available on the 82C465MV as a re g ister-pro g rammable option. lo g ic from the proven opti 82c611 local-bus ide controller is used to incorporate this option. note , however , that the write postin g and read prefetchin g features of the separate 82c611 device are not supported b y the 82C465MV chip. 4.6.4.1 hardware considerations local-bus ide support re q uires seven pins. six of the si g nals are shared si g nals that also g o to their active state ( from the perspective of the ide ) durin g non-ide c y cles. therefore , these si g nals must be q ualified b y dbe#; the y cannot be con- nected directl y to the ide interface. the si g nals are defined as follows. ? drive read ( drd# ) - provides the read strobe si g nal for the ide drive; also switches the data buffer direction toward the sd bus durin g read c y cles. the 82C465MV drives drd# on the bale line if compact isa is disabled and on tc is cisa is enabled. refer to section 4.6.5 "compact isa interface" . ?drive write ( dwr# ) - provides the write strobe si g nal for the ide drive. the 82C465MV drives dwr# on the sbhe# line. ? address bits 1:0 ( da1:0 ) - provided directl y from the 82C465MV sa1:0 si g nals. ? address bits 2 and 9 ( da2 and da9 ) - buffered version of cpu ca2 and ca9. ? address bit 7 can be used for four drive support ( mvb ) . ? drive buffer enable ( dbe# ) - enables the buffer for control lines drd# and dwr# , and address bits da9 , 2 , 1 , and 0 to the ide drive , as well as the data bus buffers. dbe# replaces the tris# si g nal on pin 176. the drd# and dwr# si g nals and the other control si g nals are separated from the standard isa bus i/o control si g nals to avoid the incompatibilit y that can occur when si g nals such as ior# and iow# are short pulsed as the y would be for an ide c y cle. short pulses on these lines can cause incorrect operation on some isa peripheral devices , even if the read and write is not intended for those devices. fi g ure 4-6 illustrates how the connections would t y picall y be made. figure 4-6 interface to integrated ide controller * drd# comes out on bale if compact isa interface is disabled. see section 4.6.5 , "compact isa interface" on pa g e 98. iochrdy sbhe# tc* sa2 sa1 sa0 sa9 dbe# 161 175 170 148 146 176 82C465MV hdchrdy dwr# da2 da1 da0 hdcs0# hdcs1# 1oe# 2oe# 74244 150 drd# sa9 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 91 revision: 3.0 4.6.4.2 performance and power enhanced ide uses the sd bus for its data transfers , but does not use isa bus transfers because of its dedicated drd# , dwr# , and dbe# si g nals. essentiall y, the local-bus ide controller can run extremel y short c y cles because all tim- in g aspects of the c y cle are directl y pro g rammable to meet the capabilities of the drive bein g used. the 82C465MV chipset implementation of local-bus ide is desi g ned to save power. the buffers to/from the ide are tristated between c y cles. therefore , no power is wasted to g - g lin g the ide data lines when the ide is not in use. an innovative method is used to handle port 3f7h [ 7 ] from the external flopp y controller. bit 7 from the fdc must be attached to bits [ 6:0 ] from the ide controller whenever an i/o read of 3f7h takes place , and normall y re q uires a separate ided7 line from the ide. on the 82C465MV , two separate c y cles take place whenever the an i/o read from 3f7h takes place. first , the local-bus ide c y cle is run usin g drd# and dbe#. then an isa bus i/o c y cle is run. when the 82C465MV returns a value to the cpu , it provides bits [ 6:0 ] read from the ide and bit 7 from the isa bus. 4.6.4.3 signal connection with the ide interface disabled , the chip pin functions remain compatible with those of the 82c463mv. when the ide inter- face is enabled , the onl y function actuall y lost is tris#. tris# serves onl y to indicate that the s y stem is in suspend mode , a status which can also be derived from the ppwr0-1 outputs. the various isa bus si g nals that are used for ide command and chip select lines are si g nals that would nor- mall y re q uire q ualification b y other si g nals; to gg led b y them- selves , the y should not cause an y action or conflicts on the isa bus. 4.6.4.4 dbe (tris) polarity the dbe# line ( or the tris# line if the ide interface is not enabled throu g h syscfg ach [ 3 ]) is normall y an active low si g nal. since this polarit y ma y not be correct for all connected devices , the polarit y can be inverted throu g h a strap option. the inversion is valid for either the tris# or the dbe# func- tion , chan g in g them to tris and dbe respectivel y . the options available are as follows. ? normal active-low sense , for dbe# ( tris# ) : do not strap tris# at reset ( internal pull-up selects option ) ? active-hi g h sense , for dbe ( tris ) : pull tris# low at reset ( can be strapped permanentl y with 10k w to g round ) 4.6.4.5 programming the controller can be enabled to respond to i/o accesses either in the 1f0-1f7h and 3f6-3f7h ran g e , or in the 170- 177h and 376-377h ran g e , but never to both. i/o port refer- ences in this document list both ran g es , but onl y one ran g e can ever be active at a time ( alwa y s selected b y syscfg ach [ 2 ] re g ardless of other mode settin g s ) . there are two wa y s to pro g ram operation of the local bus ide controller. basic timin g is the fixed timin g selection available throu g h syscfg ach [ 7:4 ] . enhanced timin g refers to the precise control provided throu g h the 611 re g ister set. easy programming method (basic) use syscfg ach [ 7:4 ] to select the cpu speed and the mode of operation. the ide controller lo g ic will g enerate commands for the correct number of cpu clocks to approxi- mate the selected mode timin g . ide interface enable syscfg ach[3] - when the ide inter- face is disabled , tris# is available. when the ide interface is enabled , pin 176 ( tris# ) becomes dbe# and tris# is no lon g er available. ppwr0-1 in their auto-to gg le mode can perform essentiall y the same function as tris#. port 3f7 decode disable syscfg ach[1] - prevents port 3f7 reads from bein g combined with ide controller reads in situations where this arran g ement causes problems. when syscfg ach [ 1 ] = 0 , 3f7h [ 7 ] comes from the isa bus; 3f7h [ 6:0 ] ( or 377h [ 6:0 ] if bit 2 = 1 ) come from local-bus ide. when syscfg ach [ 1 ] = 1 , 3f7h [ 7:0 ] come from the isa bus. table 4-76 g ives the bit formats for syscfg ach. the set- tin g in syscfg ach [ 7:4 ] will select c y cle timin g s accordin g to the scheme in table 4-77. table 4-76 ide controller configuration 76543210 syscfg ach ide interface configuration register default = 00h chipset input clock fre q uenc y : 00 = 50mhz 01 = 40mhz 10 = 33mhz 11 = 20/25mhz ide command pulse duration: 00 = 600ns 01 = 383ns 10 = 240ns 11 = 180ns ide interface: 0 = disable 1 = enable ide port address select: 0 = 1f0-7h, 3f6-7h 1 = 170-7h, 376-7h 3f7h [ 6:0 ] source: 0 = local ide 1 = isa bus reserved 82C465MV/mva/mvb opti ? pa g e 92 912-3000-016 revision: 3.0 table 4-77 automatic cycle settings available through syscfg ach[7:4] syscfg ach[7:4] expected input clock frequency (mhz) setup time (clocks) command pulse (clocks) recovery time (clocks) maximum cycle time (clocks) 0000 50 4 9 17 30 0001 3 7 10 20 0010 2 6 4 12 0011 2 5 2 9 8-bit -- 15 14 31 0100 40 3 7 14 24 0101 3 6 7 16 0110 2 5 3 10 0111 2 4 2 8 8-bit -- 12 11 25 1000 33 3 6 11 20 1001 2 5 6 13 1010 2 4 2 8 1011 1 3 2 6 8-bit -- 10 9 20 1100 25 2 5 8 15 1101 2 4 4 10 1110 1 3 2 6 1111 1 2 2 5 8-bit -- 8 6 15 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 93 revision: 3.0 precise programming method (enhanced) more precise control of ide operation is available b y usin g the 611 re g ister set , so called because it is re g ister-compat- ible with the re g ister set used in the opti 82c611 stand- alone local-bus ide controller. this re g ister set is hidden behind the ide drive i/o ports and is not normall y accessible. timing 0 and timing 1 the 611 re g ister set supports two separate ide drives on a sin g le cable with independent timin g re q uirements. applica- tion software writes bit 1f6h [ 4 ] or 176h [ 4 ] to select between drive 0 and 1 on the cable. the 611 core tracks writes to this i/o port and switches its timin g . the correspondence is not necessaril y direct , however , between drive 0 and timin g 0 , for example. each drive can select its timin g from two sources , which are themselves selectable accordin g to bit 1f3/173h [ 7 ] . basic choices when bit 1f3/173h [ 7 ] = 0: 1. the eas y method timin g s from syscfg ach [ 7:4 ] 2. timin g 0 enhanced choices when bit 1f3/173h [ 7 ] = 1: 1. timin g 1 2. timin g 0 the basic or enhanced timin g choices are made as follows. internal to the 82C465MVa , there is a sin g le 611 re g ister set. the 611 re g isters are available onl y when enabled throu g h a special unlockin g procedure. timin g choices are made accordin g to table 4-78 and table 4-79 throu g h bits 1f3/173h [ 2-3 ] for drives 0 and 1 , respectivel y . once all pro- g rammin g is complete , the 611 re g ister set a g ain becomes hidden. from then on , accesses to the ide port bit 1f6/176h [ 4 ] are tracked to determine the timin g to use. table 4-78 82C465MVa operation with primary i/o range selected table 4-79 82C465MVa operation with secondary i/o range selected syscfg ach[2] i/o range sa7 value ide drive setting (ide head/drive select register) drive selected timing selected by hidden 611 register bit 0primar y 11f6h [ 4 ] = 0 0 1f3h [ 2 ] 1f0-7h , 3f6-7h 1f6h [ 4 ] = 1 1 1f3h [ 3 ] syscfg ach[2] i/o range sa7 value ide drive setting (ide head/drive select register) drive selected timing selected by hidden 611 register bit 1 secondar y 0 176h [ 4 ] = 0 0 173h [ 2 ] 170-7h , 376-7h 176h [ 4 ] = 1 1 173h [ 3 ] 82C465MV/mva/mvb opti ? pa g e 94 912-3000-016 revision: 3.0 subset registers for timing 0 and timing 1 within the sin g le 611 re g ister set , there are two subsets of re g isters to pro g ram the read pulse width , write pulse width , read recover y time , and write recover y time sepa- ratel y for timin g 0 and timin g 1. the re g ister set loaded b y writin g to 1f0/1h or 170/1h is selected b y bit 1f6/176h [ 0 ] . settin g this bit to 0 allows writes to 1f0/1h or 170/1h to pro- g ram timin g 0; settin g the bit to 1 allows pro g rammin g of timin g 1. table 4-80 611 register set 76543210 port 1f0h/170h read cycle timing register read pulse width: the value written to these bits, plus 1, selects the drd# pulse width for a read from the 16-bit data re g ister. ( 1 ) read recover y time: the value written to these bits, plus 2, determines the minimum time allowed between the end of drd# and the start of the next ide chip select ( hdcs0-1#, derived from tc ) . ( 1 ) ( 1 ) the value indicates the width in terms of fbclkin c y cles. port 1f1h/171h write cycle timing register write pulse width: the value written to these bits, plus 1, selects the dwr# pulse width for a write to the 16-bit data re g ister. ( 1 ) write recover y time: the value written to these bits, plus 2, determines the minimum time allowed between the end of dwr# and the start of the next ide chip select ( hdcs0-1#, derived from tc ) . ( 1 ) ( 1 ) the value indicates the width in terms of fbclkin c y cles. port 1f2h/172h id register (wo) 82c611 re g ister access: 0x = enable 10 = two 1f1/171h reads to enable ( default ) 11 = permanentl y disable reserved id bits: these bits must alwa y s be written as 11. port 1f3h/173h control register 1 timin g re g ister value select: 0 = basic 1 = enhanced reserved drive 1 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 drive 0 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 reserved ide operation: 0 = disable 1 = enable port 1f5h/175h status register (ro) isa 3f7h [ 7 ] status revision number: returns 00 on present silicon revi- sion. irq14 status syscfg ach [ 5:4 ] settin g syscfg ach [ 7:6 ] settin g port 1f6h/176h secondary setup and hold timing register reserved address setup time: the value written, plus 1, selects the address setup time. ( 1 ) channel read y hold time: the value written, plus 2, selects the dela y for set- tin g the command pulse inactive from when the con- troller sees iochrdy g o hi g h. ( 1 ) timin g re g ister load select 0=timin g 0 1=timin g 1 ( 1 ) the value indicates the width in terms of fbclkin c y cles. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 95 revision: 3.0 step-by-step programming procedure each phase of 611 pro g rammin g is described below. before accessin g the 611 re g ister set , the basic interface must be set up as follows. 1. enable the external ide controller interface b y settin g syscfg ach [ 3 ] = 1. 2. select the i/o ran g e to be used throu g h syscfg ach [ 2 ] . for the purposes of this example , syscfg ach [ 2 ] is set to 0 to select the 1f0-7h and 3f6-7h ran g e. if the 170-7h and 376-7h ran g e is selected instead , use the x7x port instead of the xfx port for each of the follow- in g steps. 3. use syscfg ach [ 1 ] to select whether 3f7h accesses will be directed to the ide drive. if enabled , onl y bits [ 6:0 ] will come from the local bus ide interface; bit 7 alwa y s comes from the isa bus because it belon g s to the flopp y disk controller ( if present ) . the basic ide interface is now available. syscfg ach [ 7:4 ] can be used to select the fixed timin g s listed above. if these fixed timin g s are sufficient , there is no need to use the 611 re g ister set. enabling access to 611 register set the 611 re g ister set must be enabled throu g h a ver y specific procedure. 1. perform a word read of 1f1h two times. this operation makes the 611 re g ister set accessible for the next i/o operation. 2. write 00000011b ( 03h ) to port 1f2h. this pro g rammin g keeps the 611 re g isters accessible indefinitel y . the 611 re g ister set is now accessible. no ide operation can take place as lon g as the re g ister set access is enabled. setting up enhanced 611 timing once the 611 re g ister set is unlocked , timin g 0 and timin g 1 can be pro g rammed. 1. write x1f6h with bit 0 = 0 to be able to pro g ram timin g 0. 2. pro g ram the upper and lower nibbles of 1f0h and 1f1h with the correct values for timin g 0. the read and write pulse widths can be independentl y pro g rammed to be as short as one clock , while the recover y time for these c y cles can be as short as two clocks. 3. write 1f6h with bit 0 = 1 to be able to pro g ram timin g 1. 4. pro g ram 1f0h and 1f1h with the correct values for tim- in g 1. 5. write 1f6h with bits [ 5:1 ] set to select the re q uired address setup time and iochrdy recover y time. these values appl y to both timin g 0 and timin g 1. bit 0 can be left in an y state. the timin g sets are now pro g rammed. the next step is to assi g n one of the timin g sets to each drive. associating timing with each drive re g ister 1f3h selects timin g options for the drives , and is the last step necessar y before hidin g the 611 re g ister set and enablin g 611 operation. prepare a pro g rammin g b y te in which: 1. bit [ 7 ] =1 to enable enhanced timin g, thus allowin g both drives to select between the precise timin g sets timin g 0 and timin g 1. 2. bit [ 2 ] selects timin g 0 or timin g 1 for drive 0 , and bit [ 3 ] does the same for drive 1. 3. bit [ 0 ] = 1 to enable all of the pro g rammin g established to this point. set all other bits to 0 , and write this value to 1f3h. enabling ide operation and hiding 611 register set the 611 re g ister set must be hidden from standard access before ide operation can be g in. two options are available. ? write 1f2h with 11000011b ( c3h ) to disable 611 re g ister access and full y enable ide operation , and also prevent an y future access to the 611 re g ister set until the next hardware reset. ? write 1f2h with 10000011b ( 83h ) to disable 611 re g ister access and full y enable ide operation , but leave open the future possibilit y of accessin g the 611 re g ister set b y restartin g this whole procedure. application software can now control the drive selection and the timin g with which it will be accessed throu g h bit 1f6h [ 4 ] . 82C465MV/mva/mvb opti ? pa g e 96 912-3000-016 revision: 3.0 4.6.4.6 four-drive ide support the 82C465MV and 82C465MVa parts provide local bus ide controller lo g ic that supports two separate ide drives with independent timin g re q uirements. however , both drives must be on a sin g le cable that responds either to 1f0-7h and 3f6- 7h ( main i/o ran g e ) accesses or to 170-7h and 376-7h ( auxil- iar y i/o ran g e ) accesses. writin g bit 1f6h [ 4 ] ( main ) or 176h [ 4 ] ( auxiliar y) selects between drive 0 and 1 in the selected ran g e. internall y, there is onl y a sin g le re g ister set that is selected b y sa7 accordin g to the settin g of syscfg ach [ 2 ] . the 82C465MVb part maintains backward compatibilit y with its predecessors , but allows both the primar y and secondar y i/o ran g es to be claimed b y the ide controller; syscfg ach [ 2 ] is i g nored in this mode. the dbe# si g nal must then be q ualified b y sa7 ( with external lo g ic ) to select between the two cables. there is still j ust a sin g le set of internal re g isters that are common to both the 1fx/3fx and 17x/37x addresses , with the exception of bits 1f3h [ 3:2 ] and 173h [ 3:2 ], which are separate. in this wa y, either of the timin g sets 0 and 1 can be pro g rammed individuall y for an y of the four drives. the ach [ 5:4 ] settin g can also be used. settin g syscfg 3fh [ 5 ] =1 enables four ide drive support mode. tables 4-81 throu g h 4-83 shows the discussed pro g rammin g drive selections. table 4-81 82C465MVa operation with primary i/o range selected table 4-82 82C465MVa operation with secondary i/o range selected table 4-83 82C465MVb operation with four drive support selected syscfg ach[2] i/o range ide drive setting drive selected timing selected by 0primar y 1f6h [ 4 ] = 0 0 1f3h [ 2 ] 1f0-7h , 3f6-7h 1f6h [ 4 ] = 1 1 1f3h [ 3 ] syscfg ach[2] i/o range ide drive setting drive selected timing selected by 0primar y 1f6h [ 4 ] = 0 0 1f3h [ 2 ] 1f0-7h , 3f6-7h 1f6h [ 4 ] = 1 1 1f3h [ 3 ] i/o range ide drive setting drive sa7 timing selected by main cable 1f6h [ 4 ] = 0 0 1 1f3h [ 2 ] 1f0-7h , 3f6-7h 1f6h [ 4 ] = 1 1 1f3h [ 3 ] auxiliar y cable 176h [ 4 ] = 0 0 0 173h [ 2 ] 170-7h , 376-7h 176h [ 4 ] = 1 1 173h [ 3 ] 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 97 revision: 3.0 performance improvement bits 1f3h/173h [ 5:4 ] allow extra control over the re g ister set- tin g s normall y available at 1f0-1h/170-1h. these bits are not controlled b y syscfg 3fh [ 5 ] . table 4-84 shows the re g is- ters associated with four drive ide control. table 4-84 four drive ide control 76543210 syscfg 3fh misc. control register default = 00h four ide drive support: 0 = disable 1 = enable (mvb) port 1f3h (mvb) primary cable ide control register 1 timin g re g ister value select: 0 = basic 1 = enhanced reserved timin g 1 performance: 0 = 465mv- compatible 1 = reduce cmd. pulse 1/2 clock, recover y time 1/2 clock timin g 0 performance: 0 = 465mv- compatible 1 = reduce cmd. pulse 1/2 clock, recover y time 1/2 clock primar y cable drive 1 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 primar y cable drive 0 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 reserved ide operation: 0 = disable 1 = enable port 173h (mvb) secondary cable ide control register 1 secondar y cable drive 1 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 secondar y cable drive 0 timin g select: -basic: 0 = ach [ 5:4 ] 1 = timin g 0 -enhanced: 0 = timin g 1 1 = timin g 0 82C465MV/mva/mvb opti ? pa g e 98 912-3000-016 revision: 3.0 4.6.5 compact isa interface the 82C465MVb chipset incorporates the opti compact isa ( cisa ) interface. this interface allows connection of an y compact isa peripheral device , such as the opti 82c852 pcmcia controller. the compact isa specification is a sep- arate document that describes the interface in detail. the compact isa implementation must deal with certain issues that are specific to the interface architecture. ? atclk cannot be stopped without a specific stop clock c y cle , since cisa depends on clock ed g es to transfer interrupts. the 82C465MVb can be pro g rammed to g ener- ate this stop clock c y cle , both automaticall y and manuall y . ? the cisa interface g enerates an at backoff ( atb# ) si g - nal to the 465mvb to make an interrupt or dma re q uest. the cisa interface is re q uired to backoff an y isa c y cle it has alread y started as lon g as it has not y et asserted ale. atb# will come , at latest , one-half atclk before ale# would be asserted. once atb# is asserted , the 82C465MVb must inhibit all dma activit y and must pre- vent an eoi command to the interrupt controller from tak- in g effect until atb# is de-asserted and the new drq/irq states are latched in. ? the 82C465MVb compact isa involves two mandator y si g nals and one optional si g nal. -cmd# ( o ) - command , g enerated b y the 82C465MVb to run cisa c y cles. cmd# is on pin 173 and replaces the pio1 function on the 82C465MVb part when the cisa interface is enabled. to eliminate the need for an external keeper resistor , the 82C465MVb implements a weak pull-up on this pin until its pro g rammin g re g isters are written. a write to syscfg 57h disables the pull-up resistor. therefore , software should enable cmd# before writin g syscfg 57h. - sel#/atb# ( i ) - cisa peripheral device selected handshake input durin g isa c y cles; at backoff re q uest between c y cles; clock restart re q uest durin g idle mode. sel#/atb# is on pin 186 and replaces the ri pin on the 82C465MVb part when the cisa interface is enabled. the cisa interface re q uires a pull-up resistor on this line , which is automaticall y enabled when the sel#/atb# function is selected. - cdir ( o ) - optional cisa buffer direction si g nal. for desktop-t y pe desi g ns where the cisa si g nals are buff- ered on the motherboard to connect throu g h a lon g rib- bon cable to 82c852 pcmcia controller ( s ) . cdir is on pin 78 and replaces the ras4# function. the compact isa control re g isters syscfg f8h , f9h , and fah enable the interface and control various features. the bit formats for syscfg f8h and f9h are shown in table 4-85. refer to table 4-86 for syscfg fah bit formats. note: the compact isa interface uses the ale si g nal for all its c y cles. the 82C465MV and 82C465MVa parts also use ale as the drd# si g nal for local bus ide. therefore , when cisa is enabled , the drd# si g nal moves to tc from ale so that ale will not to gg le except on isa/cisa c y cles. use sa9 instead of tc on the ide buffer to g enerate cs0# and cs1#. table 4-85 compact isa control registers 76543210 syscfg f8h compact isa control register 1 (mvb) default = 00h inhibit mrd# and mwr# if sel# asserted on memor y c y cle? 0 = no 1 = yes inhibit mrd# and mwr# if sel# asserted on dma c y cle? 0 = no 1 = yes inhibit iord# and iowr# if sel# asserted on i/o c y cle? 0 = no 1 = yes irq15 assi g nment: 0 = irq15 1 = ri reserved fast cisa memor y c y cle: 0 = disable ( isa# = 0 ) 1 = enable ( isa#=1 ) pin 78 function: 0 = ras4# 1 = cdir compact isa interface ( reas- si g ns pins 173, 186 ) : 0 = disable 1 = enable syscfg f9h compact isa control register 2 (mvb) default = 00h spkd si g nal drivin g : 0 = alwa y s, per at spec. 1 = s y nchro- nousl y , per cisa spec. end-of-interrupt hold: dela y s 8259 reco g nition of eoi command to prevent false inter- rupts. 00 = none 01 = 1 atclk 10 = 2 atclks 11 = 3 atclks stop clock count bits cc [ 2:0 ] : stop clock c y cle indication to cisa devices of how man y atclks to expect before the clock will stop. 000 = reserved 001 = 1 atclk ( default ) ... 111 = 7 atclks generate cisa stop clock c y cle ( if not alread y stopped ) : 00 = never 01 = on stpclk# c y cles to the cpu ( hardware ) 10 = immediatel y ( software ) 11 = reserved 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 99 revision: 3.0 compact isa interface enable bit - provides master control over whole interface and enables reassi g nment on pins 173 and 186 to support cisa. if this bit is 0 , all compact isa func- tions are disabled and no address strobin g occurs on the sd bus. no other compact isa re g ister bits should be set when syscfg f8h [ 0 ] = 0. cdir pin enable bit - selects whether pin 78 will be reas- si g ned as cdir to control cisa cable driver direction. irq15 assignment - reassi g ns irq15 from the pcmcia slot so that it can g enerate a rin g indicator ( ri ) smi instead. inhibit commands if sel# asserted - these bits control whether commands will be hidden from isa bus peripheral devices if the c y cle is claimed b y a cisa device. the feature allows devices that use the same memor y or i/o space to avoid conflict with each other; cisa devices alwa y s preempt isa devices. a separate bit is provided for memor y si g nals durin g dma , which would allow fl y -b y transfers to function between a pcmcia dma card and an isa memor y device. spkd signal driving - selects the cisa scheme for shared audio outputs. refer to the cisa specification for complete information. 4.6.5.1 cisa stop clock cycle generation syscfg f9h [ 1:0 ] enable the 82C465MVb to g enerate the stop clock broadcast c y cle on the cisa bus , after which it can stop the at clock. there are two methods of g eneratin g a cisa stop clock c y cle: hardware-controlled and software- controlled. hardware cisa stop-clock control hardware-controlled cisa stop clock c y cle g eneration occurs automaticall y, if atclk has not been stopped alread y, when- ever syscfg f9h [ 1:0 ] = 01 and the 82C465MVb chip receives a stop g rant c y cle ( or stpgnt# si g nal such as suspa# ) from the cpu. the chipset g enerates a stop re q uest to the cpu when chan g in g cpu speeds or stoppin g the cpu clock; the cpu responds with a stop g rant. when syscfg f9h [ 1:0 ] = 01 to enable automatic stop clock c y cle g eneration on cisa , address phase 1 of each cisa c y cle will not be g enerated until the c y cle is decoded to be an isa c y cle. the lo g ic adds in one extra at clock before the c y cle starts to properl y start the cisa interface. inhibition of cisa phase 1 g eneration saves power b y avoidin g unneces- sar y to gg lin g on the mad bus. when syscfg f9h [ 1:0 ] = 00 to disable hardware stop clock mode , the 82C465MVb lo g ic drives address phase 1 of each cisa c y cle as soon as it detects ads# active. in this mode , there is no at clock start-up dela y . software stop-clock con- trol can still be used to stop the clock and save power. software cisa stop-clock control software-controlled cisa stop clock c y cle g eneration occurs onl y when syscfg f9h [ 1:0 ] are written to 10. a cisa stop clock c y cle is forced onto the cisa bus. whenever syscfg f9h [ 1:0 ] = 10 , syscfg f9h [ 7:2 ] written to this re g ister are i g nored so no read/modif y /write procedure is re q uired. this c y cle is g enerated onl y once; the bits then revert to their pre- vious settin g ( 00 or 01 ) . stop clock count bits cc[2:0] - indicate to cisa devices how man y atclks to expect before the clock will stop. the default settin g of one atclk is correct for most applications. 4.6.5.2 configuration cycle generation the 82C465MVb part can be pro g rammed to g enerate one cisa confi g uration c y cle , the stop clock broadcast c y cle , automaticall y after a period of inactivit y . in order to provide for future confi g uration c y cle possibilities , the 82C465MVb cisa interface also includes a g eneric command g eneration scheme. this scheme takes advanta g e of the scratchpad re g isters alread y present in the 82c465 series parts , and does not prevent their continued use as scratchpad re g isters. the y must be repro g rammed onl y in order to send out a con- fi g uration c y cle. to g enerate a confi g uration c y cle: 1. load the phase 1 word in syscfg 6c-6dh. 2. load the phase 2 word in syscfg 6e-6fh. 3. load the data phase word in syscfg 52-53h. 4. write syscfg fah [ 0 ] = 1 to run the c y cle. the cisa interface will g enerate the desired confi g uration c y cle. the c y cle will alwa y s be a broadcast ( write ) c y cle , since there is no inherent means of receivin g information back from the confi g uration c y cle. whenever syscfg fah [ 0 ] = 1 , syscfg fah [ 7:1 ] written to this re g ister are i g nored so no read/modif y /write procedure is re q uired. syscfg fah [ 0 ] is automaticall y cleared to 0 after the c y cle runs. 82C465MV/mva/mvb opti ? pa g e 100 912-3000-016 revision: 3.0 4.6.5.3 driveback cycle handling normall y the 82C465MVb will transfer the irq and drq information of an irq/drq driveback c y cle to the interrupt and dma controllers. however , syscfg fah [ 2 ] allows driveback c y cle information to simpl y be latched and an smi g enerated. in this wa y, smm code can determine how ( or whether ) to deal with the chan g ed irq or dma status. the information is latched in the new scratchpad re g isters 7-10. these new re g isters can be used for g eneral purpose stor- a g e if compact isa is disabled. pmi#36 is g enerated for this event , and is read/cleared throu g h syscfg eah [ 7 ] . table 4-86 shows the re g isters associated with cisa c y cle g eneration. table 4-86 cisa cycle generation registers 76543210 syscfg 52h scratchpad register 1 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: data phase information, low b y te (mvb) syscfg 53h scratchpad register 2 default = 00h general purpose stora g e b y te - for cisa confi g uration c y cles: data phase information, hi g h b y te ( mvb ) syscfg 6ch scratchpad register 3 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, low b y te (mvb) syscfg 6dh scratchpad register 4 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, hi g h b y te (mvb) syscfg 6eh scratchpad register 5 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, low b y te (mvb) syscfg 6fh scratchpad register 6 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, hi g h b y te (mvb) syscfg fch scratchpad register 7 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: irq phase information, low b y te ( ro ) (mvb) syscfg fdh scratchpad register 8 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: irq phase information, hi g h b y te ( ro ) (mvb) syscfg feh scratchpad register 9 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: drq phase information, low b y te ( ro ) (mvb) syscfg ffh scratchpad register 10 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: drq phase information, hi g h b y te ( ro ) (mvb) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 101 revision: 3.0 md# state during suspend - if the cisa bus devices are to be powered down durin g suspend mode , settin g syscfg fah [ 2 ] = 1 drives the cmd# line low with the same timin g as the ppwr0-1 lines so that there is no current leaka g e path. resume from suspend on sel#/atb# low - settin g syscfg fah [ 3 ] = 1 allows cisa devices in stop clock mode to resume s y stem operation b y g eneratin g an interrupt. dur- in g normal operation when cisa devices are in stop clock mode , the sel#/atb# line acts as a clkrun# si g nal. this bit also allows the same si g nal to act as rsm#. irq/drq driveback trap - if syscfg fah [ 1 ] = 1 and an irq/drq driveback c y cle occurs , syscfg eah [ 7 ] indicates that the smi was caused b y the interrupt driveback. no more irq driveback c y cles will be serviced until this pmi is cleared b y writin g syscfg eah [ 7 ] = 1. cisa sel/atb# low caused resume - if syscfg fah [ 3 ] = 1 to allow resume from sel#/atb# , syscfg 6bh [ 3 ] reads 1 to identif y the resume source as cisa. syscfg fah compact isa control register 3 (mvb) default = 00h reassi g n epmi3 as ri? 0 = no 1 = yes use in case ri is assi g ned as sel#/atb# reassi g n epmi4 as iochck#? 0 = no 1 = yes use in case iochck# is assi g ned as kbcrstin resume from suspend on sel#/atb# low: 0 = disable 1 = enable cmd# state durin g suspend: 0 = driven inac- tive ( hi g h ) 1 = driven low driveback c y cle handlin g : 0 = pass drqs and irqs 1 = latch info and g ener- ate smi confi g uration c y cle g enera- tion: 0 = no action 1 = run c y cle usin g scratchpad syscfg eah pmu source register 5 (mvb) default = 00h irq/drq driveback trap pmi#36: 0 = inactive 1 = active write 1 to clear syscfg 6bh resume source register default = 00h cisa sel#/ atb# low caused resume ( ro ) ? 0 = no 1 = yes (mvb) table 4-86 cisa cycle generation registers (cont.) 76543210 82C465MV/mva/mvb opti ? pa g e 102 912-3000-016 revision: 3.0 4.7 power management unit the 82C465MV provides a lar g e amount of pro g rammable lo g ic for mana g in g s y stem power control on the most precise of levels. the basic concepts of the 82C465MV power man- a g ement scheme involve activit y monitorin g throu g h time-out events , access events , reload events , epmi events , and interrupt events. these concepts are illustrated in fi g ure 4-7 and described in detail in the followin g sections. 4.7.1 activity monitoring activit y monitorin g is based on time-outs of countdown tim- ers , the events that can be enabled to reload the timers and dela y a time-out , g eneral access events , and the s y stem mana g ement interrupts that can be g enerated in all cases. 4.7.1.1 timers the eleven 82C465MV timer re g isters all have _timer appended to their name. ?the idle_timer times lon g periods of inactivit y across all selected s y stem peripherals to determine , for example , when a full power down ( called suspend mode ) is appro- priate. ? the doze_timer times short inactivit y intervals ( between ke y strokes , for example ) to put the s y stem in an intermediate power-savin g state called doze mode . ? the r_timer g enerates a periodic interrupt to allow s y s- tem mana g ement code to poll for activit y . ?ei g ht peripheral activit y timers are available to monitor activit y on specific peripheral devices so that s y stem man- a g ement software can put each peripheral device individu- all y into a low power mode while the rest of the s y stem continues to operate. simpl y loadin g the timer with a countdown value presets the timers. then , the next access or interrupt event starts them countin g down. a dumm y access is needed in most cases to start the timer countin g . as each timer is clocked b y its pro g rammed source , it counts down to a time-out ( zero ) which g enerates a power manage- ment interrupt ( pmi ) . the time-out pmi can , in turn , be enabled to g enerate a s y stem mana g ement interrupt ( smi ) on the smi# line that g oes from the 82C465MV to the cpu to switch it into s y stem mana g ement mode ( smm ) . figure 4-7 activity monitoring block diagram timers idle doze r lcd kbd dsk hdu com1 com2 gnr1 gnr2 time-out events group enabled irqs epmis csg0-3 lpt lcd dsk kbd hdu com1 com2 gnr1 gnr2 interrupt events epmi events access events pmi enable #6 #0-3 , 24-26 #12-15 , 20-23 #4 ( idle ) #27 ( doze ) #5 ( r ) #8-11 , 16-19 smi ( periodic timer ) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 103 revision: 3.0 4.7.1.2 events each timer has one or more events that can reload it with its ori g inal value , holdin g off the time-out. the events can be: access events , those that are caused b y cpu access to a certain i/o and/or memor y ran g e associated with that timer; or interrupt events , tri gg ered b y isa bus irq events or spe- cial external power mana g ement inputs ( epmis ) . all events can be enabled individuall y to g enerate a pmi; access events g enerate separatel y numbered pmis , while interrupt events are combined into a sin g le pmi ( pmi#6 ) . as opposed to time-out caused pmis , event pmis can be enabled to: ? reload the timer ( s ) and , if needed , restore the s y stem clocks speed ? generate an smi ? do both. because of the flexibilit y of the 82C465MV power mana g e- ment lo g ic , the interaction amon g these mechanisms can become complex. it is important to keep in mind the basic g oal of the lo g ic in order to deal with power mana g ement effectivel y . 4.7.2 timers the 82C465MV lo g ic implements eleven distinct timer cir- cuits. each timer has a clockin g source associated with it. for all but the doze_timer these are named sqw0 , sqw1 , sqw2 , or sqw3 ; the doze_timer circuit works differentl y than the rest and is described separatel y in the doze mode section of this document. table 4-88 shows the fre q uencies that can be applied to the rest of the _timer counters. the sqw0-3 timin g s are based on the sqwin input to the 82C465MV lo g ic , which can be either 32khz or 128khz as selected b y syscfg 40h [ 3 ] . syscfg 40h [ 6 ] provides a secondar y ran g e of time intervals and applies g loball y to all sqw0-3 selections. table 4-87 shows the timer control re g ister bits and the re g is- ter bit locations for each timer. the timer source is selected b y bit combinations: 00 = sqw0 , 01 = sqw1 , 10 = sqw2 , and 11 = sqw3. table 4-88 lists the ran g e of time-out dela y that can be achieved b y selectin g each swqx+syscfg 40h [ 6 ] combi- nation. table 4-87 timer control bits and clock source selection registers table 4-88 time interval choices applicable to _timer settings 76543210 syscfg 40h pmu control register 1default = 00h global timer divide: 0 = divide b y 1 1 = divide b y 4 sqwin fre q uenc y : 0 = 32khz 1 = 128khz syscfg 42h clock source register 1 default = 00h clock source for gnr_timer clock source for kbd_timer clock source for dsk_timer clock source for lcd_timer syscfg b2h clock source register 2 default = 00h clock source for hdu_timer clock source for com2_timer clock source for com1_timer clock source for gnr2_timer syscfg 68h clock source register 3 default = 00h r_timer clock source idle_timer clock source choice bits syscfg 40h[6] = 0 - no base clock divisor syscfg 40h[6] = 1 - divide base clock by 4 frequency decrement timer every: maximum delay frequency decrement timer every: maximum delay sqw0 00 32768hz 30.5 s 7.81ms 8.192khz 0.122ms 31.25ms sqw1 01 512hz 1.95ms 0.5s 128hz 7.8ms 2s sqw2 10 16hz 62.5ms 16s 4hz 0.25s 64s sqw3 11 0.5hz 2s 8.5 min. 0.125hz 8s 34 min. 82C465MV/mva/mvb opti ? pa g e 104 912-3000-016 revision: 3.0 4.7.2.1 time-out count and time-out smi the timer source re g isters listed in table 4-89 are used to load the initial time-out count. the followin g rules appl y . ? a time-out count of 5 or g reater indicates the countdown value. time-out count values 1-4 should not be used: since the lo g ic can take up to four clocks to reload a time- out count value , an invalid time-out could occur in the meantime. ?writin g a time-out count of 0 disables the timer. ? a dumm y access in the appropriate address ran g e for that timer tri gg ers countin g . from then on , additional accesses will reload the timer with its initial value and dela y a time- out. ? readin g the timer value will return onl y the value initiall y written , not the current count. this rule holds true for all but the r_timer , which does return the current count. syscfg 60h returns the initial value of r_timer. when a time-out occurs , it can onl y tri gg er an smi. re g isters listed under the enablin g of events to generate smi head- in g of the s y stem mana g ement interrupt section enable each time-out event individuall y to cause an smi. table 4-89 timer source registers 76543210 syscfg 44h lcd_timer register default = 00h time count b y te for lcd_timer - monitors lcd_access. time-out g enerates pmi#8. syscfg 45h dsk_timer register default = 00h time count b y te for dsk_timer - monitors dsk_access. time-out g enerates pmi#9. syscfg 46h kbd_timer register default = 00h time count b y te for kbd_timer - monitors kbd_access. time-out g enerates pmi#10. syscfg b4h hdu_timer register default = 00h time count b y te for hdu_timer - monitors hdu_access. time-out g enerates pmi#19. syscfg b5h com1_timer register default = 00h time count b y te for com1_timer - monitors com1_access. time-out g enerates pmi#17. syscfg b6h com2_timer register default = 00h time count b y te for com2_timer - monitors com2_access. time-out g enerates pmi#18. syscfg 47h gnr1_timer register default = 00h time count b y te for gnr1_timer - monitors gnr1_access. time-out g enerates pmi#11. syscfg b7h gnr2_timer register default = 00h time count b y te for gnr2_timer - monitors gnr2_access. time-out g enerates pmi#16. syscfg 4fh idle_timer register default = 00h time count b y te for idle_timer - monitors selected irqs and epmis. time-out g enerates pmi #4. syscfg 69h r_timer register default = 00h time count b y te for r_timer - starts to count after a non zero write to this re g ister. unlike the other timer re g isters, a read from this re g ister returns the current count. time-out g enerates pmi#5. syscfg 60h r_timer base count register (ro) default = 00h r_timer initial count 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 105 revision: 3.0 4.7.3 access events cpu memor y and i/o instructions to peripheral devices cause power mana g ement events known as access events. ? most access events g enerate an access pmi directl y, which in turn can be enabled to activate the smi input to the cpu so that the event can be serviced. ? these same events can be pro g rammed to reload an associated countdown timer , thus dela y in g a time-out pmi from occurrin g . ? still other access events can onl y cause a timer reload , and cannot directl y g enerate an smi. table 4-90 lists all of the access events and how the access can reload its associated timer and reload the idle_timer. syscfg 41h pmu control register 2 default = 00h doze_0 time-out select: 000 = 2 ms 100 = 128 ms 001 = 4 ms 101 = 512ms 010 = 8 ms 110 = 2s 011 = 32 ms 111 = 8s time count bits for doze_timer - monitors selected irqs and epmis. unlike the other timer re g isters, doze_timer uses its own time base selected b y these bits. time-out g enerates pmi#27. table 4-89 timer source registers (cont.) 76543210 table 4-90 access events and their enabling bit locations access mnemonic monitored range access pmi# enable smi on current access enable smi on next access enable reload of idle_timer lpt reads/writes in i/o address ran g es 378-fh , 278- fh , and 3b8-fh ( lpt1 , 2 , and 3 ) -- -- -- 4eh [ 5 ] com1 reads/writes in i/o address ran g e 3f8-fh. 21 deh [ 5 ] dbh [ 1 ] beh [ 4 ] com2 reads/writes in i/o address ran g e 2f8-fh. 22 deh [ 6 ] dbh [ 2 ] beh [ 5 ] dsk fdd accesses to i/o port 3f5h and/or hdd accesses to 1f0-1f7h+3f6h. syscfg 57h [ 5:4 ] determine which ran g es appl y . 13 deh [ 1 ] 5bh [ 1 ] 4eh [ 1 ] kbd reads/writes to i/o ports 060h and 064h. 14 deh [ 2 ] 5bh [ 2 ] 4eh [ 2 ] lcd reads/writes in memor y address ran g e a0000- bffffh and/or i/o address ran g e 3b0-3dfh. syscfg 43h [ 7:6 ] and 5fh [ 7:6 ] . determine which ran g es appl y . 12 deh [ 0 ] 5bh [ 0 ] 4eh [ 0 ] hdu hdu accesses in the inte g rated ide controller ran g e: 1f0-7h + 3f6h ( primar y) or 170-7h + 376h ( secondar y) . syscfg ach [ 2 ] determines which addresses appl y . 23 deh [ 7 ] dbh [ 3 ] beh [ 2 ] csg0 defined in syscfg 4ah [ 7:0 ], 4bh [ 7:0 ], bfh [ 4 , 0 ] -- -- -- 4eh [ 6 ] csg1 defined in syscfg 4ch [ 7:0 ], 4dh [ 7:0 ], bfh [ 5 , 1 ] -- -- -- 4eh [ 7 ] csg2 defined in syscfg bch [ 7:0 ], bdh [ 7:0 ], bfh [ 6 , 2 ] -- -- -- beh [ 6 ] 82C465MV/mva/mvb opti ? pa g e 106 912-3000-016 revision: 3.0 note: enabled access events , except for the gnrx , comx , and csg events , can be g loball y enabled to reload the doze_timer b y settin g syscfg 41h [ 1 ] = 1. refer to the doze mode section for details. 4.7.3.1 serial (comx) and parallel port (lpt) access accesses to the lpt1 , lpt2 , and lpt3 i/o ran g e g roup can be pro g rammed to reload the idle_timer. for a g reater de g ree of control , com1 and com2 can individuall y be enabled to cause com1_access or com2_access , reload the com1_timer or com2_timer , and reload the idle_timer. 4.7.3.2 isa bus floppy and hard drive access dsk_access can come from either or both of two separate access t y pes. if enabled , the dsk_access will reload the dsk_timer , and the idle_timer as well if desired. ? flopp y accesses to i/o port 3f5h g enerate dsk_access if syscfg 57h [ 5 ] = 0. ? hard disk accesses to 1f0-1f7h and 3f6h g enerate dsk_access if syscfg 57h [ 4 ] = 0. both isa bus ide accesses and vl-bus ide accesses w ill g enerate the access event. table 4-91 shows the above mentioned re g ister bits. two separate and independent hard disk drives can be man- a g ed if the primar y drive is on the isa bus or vl bus and the secondar y drive is mana g ed b y the inte g rated ide controller. refer to the hdu_access event re g ardin g access events from the inte g rated local-bus ide controller. 4.7.3.3 integrated controller hard drive access accesses to the inte g rated hard disk controller , in the primar y ran g e ( 1f0-1f7h and 3f6h ) or the secondar y ran g e ( 170- 177h and 377h ) can cause an hdu_access , reload the hdu_timer , and reload the idle_timer. syscfg ach [ 2 ] determines which addresses appl y ( see table 4-92 ) hdu_access is based solel y on the decodin g for the inter- nal ide controller. it is independent of the dsk_access decodin g . therefore , syscfg 57h [ 4 ] does not affect hdu_access. dsk_access can continue to monitor both flopp y disk and primar y external hard disk accesses if desired. 4.7.3.4 keyboard access ke y board accesses to i/o ports 060h and 064h can cause kbd_access , reload the kbd_timer , and reload the idle_timer. table 4-91 floppy and hard drive dsk_access control csg3 defined in syscfg bah [ 7:0 ], bbh [ 7:0 ], bfh [ 7 , 3 ] -- -- -- beh [ 7 ] gnr1 defined in syscfg 48h [ 7:0 ], 49h [ 7:0 ], and aeh [ 4 , 2 , 0 ] 15 deh [ 3 ] 5bh [ 3 ] 4eh [ 3 ] gnr2 defined in syscfg b8h [ 7:0 ], b9h [ 7:0 ], and aeh [ 5 , 3 , 1 ] 20 deh [ 4 ] dbh [ 0 ] beh [ 3 ] table 4-90 access events and their enabling bit locations (cont.) access mnemonic monitored range access pmi# enable smi on current access enable smi on next access enable reload of idle_timer 76543210 syscfg 57h pmu control register 6 default = 00h dsk_access includes fdd? 0 = yes 1 = no dsk_access includes hdd? 0 = yes 1 = no 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 107 revision: 3.0 table 4-92 ide port address select bit 4.7.3.5 lcd controller access video controller accesses are defined as accesses to i/o ports 3b0-3dfh and to memor y locations a0000-bffffh if not masked b y syscfg 43h [ 7:6 ] . the enabled accesses cause lcd_access , reload the lcd_timer , and reload the idle_timer if not masked in syscfg 5fh [ 7:6 ] . generate boff# (ahold) on next access trap. when the lcd_timer has timed out and the next access feature has been enabled on memor y access , the memor y access cannot easil y be trapped. usuall y, the access takes place to a dead lcd subs y stem. smi occurs but does not g et ser- viced until several instructions later. when syscfg d5h [ 0 ] = 1 , a next access to the lcd causes the 82C465MV lo g ic to g enerate ahold before g en- eratin g smi. if the ahold si g nal is externall y g ated to g ener- ate a boff# si g nal ( as for l1 writeback cache control ), the boff# si g nal should force the cpu to move back to the start of the current instruction. after smi is asserted , boff# ( ahold ) is de-asserted. dependin g on the cpu lo g ic , this procedure mi g ht convince the cpu to perform the smi ser- vice first. if so , the video subs y stem can be completel y pow- ered down on a backli g ht time-out and restored without losin g characters on the next video access. table 4-93 shows the above mentioned re g ister bits. table 4-93 lcd controller access control 76543210 syscfg ach ide interface configuration register default = 00h ide port address select: 0 = 1f0-7h, 3f6-7h 1 = 170-7h, 376-7h 76543210 syscfg 43h pmu control register 4 default = 00h lcd_access includes i/o ran g e 3b0h- 3dfh? 0 = yes 1 = no lcd_access includes mem- or y a0000- bffffh? 0 = yes 1 = no syscfg 5fh pmu control register 7 default = 00h lcd_access includes isa bus video access? 0 = yes 1 = no lcd_access includes vl- bus video access? 0 = no 1 = yes syscfg d5h resistor control register 2 default = 00h generate boff# ( ahold ) on next access trap: 0 = disable 1 = enable 82C465MV/mva/mvb opti ? pa g e 108 912-3000-016 revision: 3.0 4.7.3.6 chip select generation (csg) access the csg0-3# lines can be pro g rammed to g enerate a chip select based on either memor y or i/o decodin g of reads and/or writes. even if the external lo g ic necessar y to imple- ment the chip select lines is not in place , the chip select events themselves can be individuall y enabled to reload the idle_timer throu g h syscfg 4eh [ 7:6 ] and beh [ 7:6 ] ( refer to table 4-94 ) . table 4-94 csg access control bits 4.7.3.7 general purpose (gnr) access two pro g rammable ran g es , gnr1 and gnr2 , are provided , each with its own separate timer , to allow an y two i/o or memor y ran g es to be monitored. as an example , the com3 i/o ran g e 3e8-3efh could be monitored for reads and writes in order to determine whether the connected uart was in active use. as another example , a network card that uses memor y in the d800-dfffh half-se g ment could be moni- tored to determine whether the memor y is bein g accessed re g ularl y and , if not , a q uer y could be sent throu g h the net- work to ensure that the connection was still valid. memory watchdog feature the 82C465MV g eneral-purpose access re g ister sets , gnr1 and gnr2 , can be monitored for activit y and can g enerate an smi when no activit y has occurred in a g iven amount of time. as an option , either or both of these re g ister sets can be assi g ned to monitor memor y space instead. in this case , instead of the bit values correspondin g to i/o address bits a [ 9:0 ], the values correspond to memor y address bits a [ 23:14 ] . the bits that select i/o read or i/o write c y cles instead indicate memor y read or memor y write c y cles. example: to monitor memor y write activit y in the 16kb block from cc00:0 to cc00:3fff re q uires first viewin g the cc00 se g - ment value as 0000 1100 1100 0000 0000 0000 to determine the value of the upper 10 bits , ca [ 23:14 ], which is 0000110011 to write into the a [ 9:0 ] gnr address decode bits. the bits are set b y writin g : ? syscfg b8h ( a [ 8:1 ]) = 00011001b , or 19h ? syscfg b9h ( a9 + write decode + read decode + a [ 5:1 ] mask bits ) = 01000000b , or 40h ? syscfg aeh ( gnr2 c y cle + gnr1 c y cle + gnr2 a0 + gnr1 a0 + gnr2 a0 mask + gnr1 a0 mask ) = 011000b , or 18h ( gnr1 values must also be considered ) . the timer values must then be entered , the pmi enabled , and then a dumm y write access must be made to the cc000- cffffh ran g e to start gnr2_timer. if no accesses are occurrin g, the timer will eventuall y expire and g enerate an smi. if enabled , the next write access to this ran g e will also cause an smi and will rel oad the timer. 76543210 syscfg 4eh idle reload event enable register 1 default = 00h csg1_ access: 0 = disable 1 = enable csg0_ access: 0 = disable 1 = enable syscfg beh idle reload event enable register 2 default = 00h csg3_ access: 0 = disable 1 = enable csg2_ access: 0 = disable 1 = enable 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 109 revision: 3.0 table 4-95 general purpose access 1 registers table 4-96 general purpose access 2 registers 76543210 syscfg 48h gnr1 base address register default = 00h gnr1_access base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 49h gnr1 control register default = 00h gnr1 base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable gnr1 mask bits for address a [ 5:1 ] ( i/o ) or a [ 19:15 ] memor y : a '1' in a particular bit means that the correspondin g syscfg 48h [ 4:0 ] is not compared. this is used to determine address block size. syscfg aeh gnr_access feature register default = 03h gnr1 c y cle decode t y pe: 0 = i/o 1 = memor y gnr1 base address: a0 ( i/o ) a14 ( memor y) gnr1 mask bit: a0 ( i/o ) a14 ( memor y) 76543210 syscfg b8h gnr2 base address register default = 00h gnr2_access base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg b9h gnr2 control register default = 00h gnr2 base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable gnr2 mask bits for address a [ 5:1 ] ( i/o ) or a [ 19:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg b8h [ 4:0 ] is not com- pared. this is used to determine address block size. syscfg aeh gnr_access feature register default = 03h gnr2 c y cle decode t y pe: 0 = i/o 1 = memor y gnr2 base address: a0 ( i/o ) a14 ( memor y) gnr2 mask bit: a0 ( i/o ) a14 ( memor y) 82C465MV/mva/mvb opti ? pa g e 110 912-3000-016 revision: 3.0 memory watchdog feature extension the 82C465MVa part provides extended g ranularit y for the memor y watchdo g function of gnr1 and gnr2. in the 82C465MV part , the gnr re g isters provide bits a [ 23:14 ] for a minimum monitorin g ran g e of 16kb. the 82C465MV lo g ic extends these re g isters b y providin g address and mask bits for a [ 13:2 ] for a minimum monitorin g ran g e of 4 b y tes. when these re g isters are used to extend the existin g i/o decodin g re g isters , the y override the settin g of the 10/16-bit i/o decodin g syscfg a0h [ 7 ] . in other words , even if syscfg a0h [ 7 ] = 1 such that upper address bits must be zero , the gnr1 and gnr2 re g isters still decode the full 16 bits of the address as lon g as those upper bits are not masked off ( default ) . these new re g isters are completel y i g nored until at least one of them is written in order to maintain compatibilit y with the 82C465MV part. once an y of re g isters at syscfg 70-75h is written , the y must all be written. this rule is especiall y impor- tant for the mask bits: address comparison would normall y be masked for memor y c y cles , but unmasked for i/o c y cles , to maintain backward compatibilit y . therefore , there is no clear default available and the re g ister values must alwa y s be writ- ten explicitl y . note that on both the 82C465MV and 82C465MVa parts , the memor y watchdo g feature cannot detect access b y a local bus master other than the cpu , nor b y an isa bus master. table 4-97 memory watchdog feature extension registers 76543210 syscfg 70h gnr1 control register 2 default = 00h gnr1_access base address: (mva) -a [ 13:6 ] for memor y watchdo g -a [ 15:10 ] for i/o ( ri g ht-ali g ned ) syscfg 71h gnr1 control register 3 default = 00h gnr1_access mask bits: (mva) - mask for a [ 13:6 ] for memor y watchdo g - mask for a [ 15:10 ] for i/o ( ri g ht-ali g ned ) syscfg 72h gnr1 base address register 4 default = 00h gnr1_access base address: (mva) -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o gnr1_access mask bits: (mva) - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o syscfg 73h gnr1 control register 2 default = 00h gnr2_access base address: (mva) -a [ 13:6 ] for memor y watchdo g -a [ 15:10 ] for i/o ( ri g ht-ali g ned ) syscfg 74h gnr1 control register 3 default = 00h gnr2_access mask bits: (mva) - mask for a [ 13:6 ] for memor y watchdo g - mask for a [ 15:10 ] for i/o ( ri g ht-ali g ned ) syscfg 75h gnr1 base address register 4 default = 00h gnr2_access base address: (mva) -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o gnr2_access mask bits: (mva) - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 111 revision: 3.0 improved memory watchdog range the memor y watchdo g feature of the 82C465MVa can decode with four-b y te g ranularit y . the 82C465MVb part allows reassi g nment of this g ranularit y so that the decode bits can extend to the full addressin g ran g e of the chip. on the 82C465MVa part , onl y addresses up to 16mb can be decoded and then the decode repeats throu g hout the s y stem address space. syscfg aeh [ 7:6 ] control this feature as shown in table 4- 98. 4.7.4 activity tracking the activit y trackin g re g ister at syscfg dfh allows events to be fla gg ed even if the y are not pro g rammed to g enerate an smi. in this wa y, code can check whether a ke y stroke occurred since the last time the re g ister was checked , for example , without actuall y g eneratin g an smi for ever y ke y - stroke. the activit y trackin g re g ister ( shown in table 4-99 ) records activit y on all ei g ht access events. no t y pe of enablin g is needed for an y of these events to be re g istered. readin g this re g ister returns fla g s indicatin g whether an y of the events has taken place and automaticall y resets the entire re g ister. the re g ister can be written if desired to set the selected bits. in this wa y, a read-modif y -write code se q uence can be used to clear selected bits onl y . table 4-98 memory decoding control bits table 4-99 activity tracking registers 76543210 syscfg aeh gnr_access feature register default = 03h gnr2 memor y decodin g : 0 = a [ 5:2 ] 1 = a [ 31:24 ] (mvb) gnr1 memor y decodin g : 0 = a [ 5:2 ] 1 = a [ 31:24 ] (mvb) syscfg 72h gnr1 base address register 4 default = 00h gnr1_access base address (mvb) : -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o *in mvb, if syscfg aeh [ 6 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 6 ] = 1. gnr1_access mask bits (mvb) : - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o *in mvb, if syscfg aeh [ 6 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 6 ] = 1. syscfg 75h gnr1 base address register 4 default = 00h gnr2_access base address (mvb) : -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o *in mvb, if syscfg aeh [ 7 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 7 ] = 1. gnr2_access mask bits (mvb) : - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o *in mvb, if syscfg aeh [ 7 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 7 ] = 1. 76543210 syscfg dfh activity tracking register default = 00h hdu_ access activit y ? 0 = no 1 = yes com2_ access activit y ? 0 = no 1 = yes com1_ access activit y ? 0 = no 1 = yes gnr2_ access activit y ? 0 = no 1 = yes gnr1_ access activit y ? 0 = no 1 = yes kbd_ access activit y ? 0 = no 1 = yes dsk_ access activit y ? 0 = no 1 = yes lcd_ access activit y ? 0 = no 1 = yes 82C465MV/mva/mvb opti ? pa g e 112 912-3000-016 revision: 3.0 4.7.5 reloading idle_timer the 82C465MV provides the idle_timer to monitor s y s- tem-wide activit y : i/o and memor y accesses b y the cpu , irqs from at peripherals , and epmis from power control and mana g ement subs y stems. the occurrence of an enabled event in an y one of these areas will reload the idle_timer. once there is inactivit y for a sufficientl y lon g time , the idle_timer will expire. expiration of the idle_timer g enerates pmi#4 , which can be enabled to g enerate an smi to inform s y stem mana g e- ment code that the s y stem is idle and that entr y into suspend mode is appropriate. refer to the suspend mode section in this document for complete information. expiration of the idle_timer cannot cause automatic ( hardware-controlled ) entr y into suspend mode , since important cpu processin g could be interrupted. the re g ister bits that enable each event individuall y to reload the idle_timer and dela y entr y into suspend mode are shown in table 4-100. syscfg 63h and a3h are write-onl y ; reads return no useful information. table 4-100 idle reload source registers 4.7.6 external pmi events the 82C465MV lo g ic can monitor a variet y of inputs that are directl y related to low-power , batter y -operated s y stem desi g ns. table 4-101 lists the external power mana g ement input ( epmi ) pins provided. note that all pins included here are considered external pmi pins , not j ust pins epmi1-4. 76543210 syscfg 4eh idle reload event enable register 1 default = 00h csg1_ access: 0 = disable 1 = enable csg0_ access: 0 = disable 1 = enable lpt_ access: 0 = disable 1 = enable gnr1_ access: 0 = disable 1 = enable kbd_ access: 0 = disable 1 = enable dsk_ access: 0 = disable 1 = enable lcd_ access: 0 = disable 1 = enable syscfg beh idle reload event enable register 2 default = 00h csg3_ access: 0 = disable 1 = enable csg2_ access: 0 = disable 1 = enable com2_ access: 0 = disable 1 = enable com1_ access: 0 = disable 1 = enable gnr2_ access: 0 = disable 1 = enable hdu_ access: 0 = disable 1 = enable syscfg 63h idle time-out select register 1 default = 00h epmi1 level-tri gg ered: 0 = disable 1 = enable irq13: 0 = disable 1 = enable irq8: 0 = disable 1 = enable irq7: 0 = disable 1 = enable irq5: 0 = disable 1 = enable irq4: 0 = disable 1 = enable irq3: 0 = disable 1 = enable irq0: 0 = disable 1 = enable syscfg a3h idle time-out select register 2 default = 00h irq15: 0 = disable 1 = enable irq14: 0 = disable 1 = enable irq12: 0 = disable 1 = enable irq11: 0 = disable 1 = enable irq10: 0 = disable 1 = enable irq9: 0 = disable 1 = enable irq6: 0 = disable 1 = enable irq1: 0 = disable 1 = enable table 4-101 external pmi source summary name description lowbat activit y on low batter y pin llowbat activit y on ver y low batter y pin epmi1 activit y on external power mana g ement input 1 epmi2 activit y on external power mana g ement input 2 epmi3 activit y on external power mana g ement input 3 epmi4 activit y on external power mana g ement input 4 table 4-101 external pmi source summary (cont.) name description 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 113 revision: 3.0 4.7.6.1 suspend/resume pin the susp/rsm pin can be pro g rammed to g enerate a pmi when chan g ed from hi g h-to-low. syscfg 61h [ 5:4 ] select the debounce lo g ic applied to the pin. 00 active low, edge triggered pmi. pmi#7 is tri gg ered on an y hi g h-to-low ed g e of susp/rsm. once the pmi is tri gg ered , software must write syscfg 5ch [ 7 ] = 1 to clear pmi#7 and deassert smi#. to resume: once the s y stem is in suspend mode , the next hi g h-to-low ed g e on susp/rsm will resume opera- tion. 01 active low, level-controlled pmi. settin g susp/rsm low causes pmi#7 to g o active; settin g susp/rsm hi g h causes pmi#7 to g o inactive. there is no latchin g associ- ated with this function , so it is not necessar y to write syscfg 5ch [ 7 ] = 1 to deassert the smi#. to resume: a low si g nal on susp/rsm g enerates a resume function. therefore , hardware/software must ensure that susp/rsm is hi g h before g oin g into sus- pend mode; otherwise , the s y stem will resume immedi- atel y . 10 active high, level-sampled pmi in 16ms. susp/rsm must be sampled hi g h for at least three 4ms clock ed g es before bein g reco g nized as a pmi. therefore , it takes a maximum of 16ms for the susp/rsm re q uest to be rec- o g nized. once the pmi is tri gg ered , software must write syscfg 5ch [ 7 ] = 1 to clear pmi#7 and deassert smi#. also , the susp/rsm pin must be sampled low for four clock ed g es ( 20ms maximum ) before the circuit is rearmed to g enerate the next pmi#7. to resume: once the s y stem is in suspend mode , a hi g h level sampled on susp/rsm for three 4ms clocks will resume operation. 11 active high, level-sampled pmi in 32ms. same as above , but the samplin g clock is 8ms instead of 4ms. therefore , susp/rsm must be sampled hi g h for a max- imum of 32ms before bein g reco g nized as a pmi , and must remain low for 40ms before the circuit is re-armed. to resume: once the s y stem is in suspend mode , a hi g h level sampled on susp/rsm for three 8ms clocks will resume operation. this makes the susp/rsm function much more practical in a desi g n where the switch is set to one specific level to com- mand suspend mode , and to the other level to command resume mode. example a notebook desi g n incorporates a lid switch that normall y leaves susp/rsm low durin g operation. syscfg 61h [ 5:4 ] are normall y set to 11. when the lid is closed , susp/rsm g oes hi g h. the chip asserts smi# 32ms later. software services the smi and rec- o g nizes pmi#7 active. the software then prepares the s y s- tem for suspend mode , and reprograms syscfg 61h [ 5:4 ] = 00 to prepare for resumin g . finall y, the software writes syscfg 50h [ 0 ] = 1 to en g a g e suspend mode. later the lid is raised and susp/rsm g oes low. because syscfg 61h [ 5:4 ] = 00 , the hi g h-to-low ed g e on susp/rsm g enerates a resume and pmi#7. software then writes syscfg 61h [ 5:4 ] back to 11 , clears pmi#7 b y writin g syscfg 5ch [ 7 ] = 1 , and returns to normal operation. 4.7.6.2 epmi signal relocation the 82C465MV offers several pin confi g uration options. in g eneral , the epmi-t y pe pins are the first to be relocated because the y need not be monitored constantl y ; the y can all be g rouped to g ether and monitored one at a time on a peri- odic basis. the possibilities are described in the pro g ram- selected interface options section of this document. resume susp/rsm input has been to gg led while in suspend suspend susp/rsm input has been to gg led while s y stem is active ri activit y detected on ri table 4-101 external pmi source summary (cont.) name description 82C465MV/mva/mvb opti ? pa g e 114 912-3000-016 revision: 3.0 4.7.6.3 programming the chipset re g isters listed in table 4-102 are used to initial- ize the epmi pins and enable them to cause pmi events. emergency overtemp sense enable - settin g syscfg a1h [ 2 ] = 1 allows a level on the epmi2 pin to force the chip into cool-down clockin g mode as set b y the thermal man- a g ement re g isters. the thermal mana g ement feature itself does not need to be enabled to use this sense function. the polarit y of the input is determined b y syscfg 40h [ 2 ] . once written to 1 , this bit cannot be cleared without a hardware reset. epmi1-2 status latch - settin g syscfg a1h [ 0 ] = 1 allows the epmi1-2 pmi events to be latched. the status returned b y syscfg 5ch [ 2:1 ] is also latched. writin g these same bits to 1 clears the status bits. note that settin g syscfg a1h [ 0 ] = 0 retains 82c463mv-compatible operation. table 4-102 epmi programming registers 76543210 syscfg 40h pmu control register 1default = 00h global timer divide: 0 = divide b y 1 1 = divide b y 4 llowbat polarit y : 0 = active hi 1 = active low lowbat polarit y : 0 = active hi 1 = active low epmi2 polarit y : 0 = active hi 1 = active low epmi1 polarit y : 0 = active hi 1 = active low syscfg dbh next access event generation register 2 default = 00h external epmi4 pin polarit y : 0 = active hi 1 = active low external epmi3 pin polarit y : 0 = active hi 1 = active low syscfg 43h pmu control register 4 default = 00h lowbat pin sample rate, g enerates pmi each time sampled active: 00 = 32s 01 = 64s 10 = 128s 11 = reserved syscfg 61h debounce register default = 00h lowbat, llowbat debounce rate select: 00 = no debounce 01 = 250 s 10 = 8ms 11 = 500ms susp/rsm debounce rate select: 00 = active low, ed g e-tri gg ered pmi 01 = active low, level-controlled pmi 10 = active hi g h, level-sampled pmi in 16ms 11 = active hi g h, level-sampled pmi in 32ms for further decode details, refer to section 4.7.6.1, "sus- pend/resume pin" on pa g e 113 syscfg a1h feature control register 2 default = 00h pin 88 - for epmi3-4: 0 = drq2 1 = epmmux emer g enc y overtemp sense: 0 = disable 1 = enable epmi1-2 status latch: 0 = d y namic 1 = latched 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 115 revision: 3.0 notes: 1 ) epmi1 and epmi2 need to be asserted until reco g nized b y its smi service routine , since these pmis are not latched unless a1h [ 0 ] = 1. 2 ) if epmi1 and epmi2 are used to place the s y stem into suspend , the epmix si g nal must be de-asserted before the suspend command ( settin g bit 50h [ 0 ] = 1 ) is written unless bit a1h [ 0 ] = 1. 4.7.6.4 power management event status the power mana g ement input pins can be monitored for their instantaneous state in the 82C465MV. this feature can be used to poll for power mana g ement status without g eneratin g an smi. the bits of the power mana g ement event status re g ister return instantaneous pin status; the state is not latched. however , since the state of some of these pins is read throu g h a multiplexer , the value from the multiplexer is held for the duration of the multiplexer c y cle. inputs that chan g e state in less than the 280ns c y cle time of the multi- plexer ma y not be indicated accuratel y throu g h this re g ister. the bits return 0 if the input is inactive , 1 if the input is active. table 4-103 power management event status syscfg 5ch pmi source register 1 (write 1 to clear) default = 00h pmi2, epmi2: 0 = inactive 1 = active pmi1, epmi1: 0 = inactive 1 = active table 4-102 epmi programming registers 76543210 76543210 syscfg dah power mgt. event status register (ro) default = 00h reserved: mask when readin g reserved: mask when readin g lowbat state: 0 = inactive 1 = active llowbat state: 0 = inactive 1 = active epmi4 state: 0 = inactive 1 = active epmi3 state: 0 = inactive 1 = active epmi2 state: 0 = inactive 1 = active epmi1 state: 0 = inactive 1 = active 82C465MV/mva/mvb opti ? pa g e 116 912-3000-016 revision: 3.0 4.8 system management interrupt (smi) most modern 80x86 processors offer a s y stem mana g ement interrupt ( smi ) that allows external lo g ic to si g nal to the cpu that a hi g h-priorit y event has occurred and must be serviced but should not in an y wa y interfere with the application cur- rentl y bein g processed. when the cpu senses its smi input active , it saves the context of its current application and loads the context of its s y stem mana g ement mode ( smm ) handler routine from a protected part of ram. smm code can then proceed to determine the reason for the interrupt , service it appropriatel y, and return to application processin g throu g h a special resume instruction that restores the context as it ori g inall y was before the smi. entr y to and exit from smm is completel y hardware-controlled. the 82C465MV handles up to 28 power mana g ement inter- rupt ( pmi ) events that can be selectivel y enabled to cause an smi to the cpu. since some of these pmi events are actuall y a sin g le indication from a g roup of events ( such as a sin g le pmi#6 that indicates whether an y of the selected irq lines has g one active ), the effective number of events that can be indicated is actuall y much g reater than 28. the pmi events that can be pro g rammed to g enerate an smi are listed in table 4-104 , table 4-105 , and table 4-106. table 4-104 irq and epmi smi sources source pmi name description #3 lowbat activit y on low batter y pin #0 llowbat activit y on ver y low batter y pin #1 epmi1 activit y on external power mana g ement input 1 #2 epmi2 activit y on external power mana g ement input 2 #24 epmi3 activit y on external power mana g ement input 3 #25 epmi4 activit y on external power mana g ement input 4 #26 ri selected count activit y detected on ri #7 susp/rsm susp/rsm input has been to gg led #6 intrgrp - or - rsmgrp an interrupt from the intrgrp set has occurred while the s y stem was runnin g, - or - an interrupt from the rsmgrp has occurred and resumed the s y stem from suspend mode 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 117 revision: 3.0 table 4-105 time-out event smi sources table 4-106 access event smi sources source pmi name description #4 idle_timer idle_timer has timed out due to no i/o activit y #27 doze_timer doze_timer has timed out due to inactivit y of selected devices #5 r_timer r_timer has timed out on its normal periodic basis #8 lcd_timer lcd timer has timed out because of no lcd activit y #9 dsk_timer flopp y ( and/or external hard ) disk timer has timed out because of no activit y #19 hdu_timer timeout has occurred because no access has occurred in the internal ide ran g e #10 kbd_timer ke y board timer has timed out because of no controller accesses #11 gnr1_timer timeout has occurred because the memor y or i/o ran g e selected b y gnr1 has had no activit y #16 gnr2_timer timeout has occurred because the memor y or i/o ran g e selected b y gnr2 has had no activit y #17 com1_timer timeout has occurred because no access has occurred in the com1 ran g e #18 com2_timer timeout has occurred because no access has occurred in the com2 ran g e source pmi name description #14 kbd_access ke y board controller has been accessed , either before or after timer timeout dependin g on current/next access settin g #12 lcd_access lcd controller has been accessed , either before or after timer time-out dependin g on current/next access settin g #13 dsk_access flopp y ( or external hard ) disk controller has been accessed , either before or after timer timeout dependin g on current/next access settin g #23 hdu_access internal ide has been accessed , either before or after timer time-out dependin g on current/next access settin g #15 gnr1_access gnr1 ran g e has been accessed , either before or after timer time-out dependin g on current/next access settin g #20 gnr2_access gnr2 ran g e has been accessed , either before or after timer time-out dependin g on current/next access settin g #21 com1_access com1 has been accessed , either before or after timer timeout dependin g on current/next access settin g #22 com2_access com2 has been accessed , either before or after timer timeout dependin g on current/next access settin g 82C465MV/mva/mvb opti ? pa g e 118 912-3000-016 revision: 3.0 4.8.1 smi presetting for various cpu type the 82C465MV lo g ic provides features to handle most t y pes of smm handlin g commonl y in use. therefore , presettin g smi operation for various processors involves several different concepts of s y stem mana g ement mode entr y, exit , and activ- it y . for all cpus with smi support , settin g syscfg 30h [ 3 ] = 1 allows relocation of cpu- g enerated addresses durin g s y stem mana g ement mode ( smm ) . the two 64kb dram se g ments at a000h and b000h are used to provide this relocated space , because these address ran g es correspond to shadow memor y of video access ran g es which are alwa y s redirected to the vl bus or isa bus an y wa y . the dram at these loca- tions would otherwise g o unused. settin g s of the other smi initialization re g isters shown in var y accordin g to cpu t y pe. su gg ested settin g s for the most pop- ular cpus are described in the sections that follow. table 4-107 smi initialization registers 76543210 syscfg 30h control register 1 default = 40h smi address relocation: 0 = disable 1 = enable syscfg 5bh pmu event register 4 default = 00h smi to irq15: 0 = disable 1 = enable smi t y pe: 0 = intel 1 = other syscfg 6bh resume source register default = 00h pin 135 function: 0 = flush# 1 = smirdy# syscfg a0h feature control register 1 default = 00h allow sreset in smm: 0 = enable 1 = disable syscfg afh smbase register default = 34h smm se g ment to be mapped to b000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 3h ) smm se g ment to be mapped to a000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 4h ) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 119 revision: 3.0 4.8.1.1 intel sl-enhanced and amd 5x86 cpu settings the intel sl-enhanced series cpus and amd 5x86 series cpus use the smiact# pin to indicate operation in smm. these cpus g enerate addresses in the 3000h and 4000h se g ments to execute smm code and access smm data. to preset operation for these cpus , pins 13 and 23 must be sensed hi g h at hardware reset time as described in section 3.3 "strap-selected interface options" . then , the re g ister bits must be set as follows. 1. set syscfg 5bh [ 7 ] = 0 to disable reroutin g of smi to irq15. 2. set syscfg 5bh [ 4 ] = 0 to enable intel-t y pe handlin g of smm. this settin g selects the smi# pin for output onl y and defines pin 136 as smiact#. 3. set syscfg a0h [ 2 ] = 1 to prevent sreset from occur- rin g within smm. intel and amd cpus re q uire sreset to be blocked durin g smm. 4. set syscfg afh [ 7:4 ] to the cpu code se g ment smbase; these bits default to 3h for the 3000h se g - ment. when in smm , cpu accesses to the selected code se g ment will map to the dram at b000h. 5. set syscfg afh [ 3:0 ] to the cpu data se g ment smbase; these bits default to 4h for the 4000h se g - ment. when in smm , cpu accesses to the selected data se g ment will map to the dram at a000h. 6. finall y, set syscfg 30h [ 4 ] = 1 to enable the smm remappin g scheme. proceed to section 4.8.2 , "loading initial smm code and data" on pa g e 120. 4.8.1.2 cyrix cpu settings current c y rix cpus use the smiads# pin to indicate whether the y are currentl y executin g smm code. these cpus g ener- ate addresses in the 6000h and 7000h se g ments to execute smm code and access smm data. to preset operation for these cpus , pins 13 and 23 must be sensed hi g h at hard- ware reset time as described in the section 3.3 , "strap- selected interface options" on pa g e 5. then , the re g ister bits must be set as follows. 1. set syscfg 5bh [ 7 ] = 0 to disable reroutin g of smi to irq15. 2. set syscfg 5bh [ 4 ] = 1 to confi g ure the smi# pin as bidirectional and define pin 136 as smiads#. 3. set syscfg 6bh [ 6 ] = 1 to enable pin 135 as smirdy# for all c y rix and ti cpus except for the c y rix cx486dx , which does not re q uire smirdy# but does re q uire flush#. 4. set syscfg a0h [ 2 ] = 1 to prevent sreset from occur- rin g within smm if desired. 5. set syscfg afh [ 7:4 ] to 7h for the cpu code se g ment smbase , which is 7000h on the c y rix 486s/s2 and ti cpus. when in smm , cpu accesses to the selected code se g ment will map to the dram at b000h. 6. set syscfg afh [ 3:0 ] to 6h for the cpu data se g ment smbase , which is 6000h on the 486s/s2 cpu. when in smm , cpu accesses to the selected data se g ment will map to the dram at a000h. 7. finall y, set syscfg 30h [ 4 ] = 1 to enable the smm remappin g scheme. proceed to section 4.8.2 , "loading initial smm code and data" on pa g e 120. 4.8.1.3 amd 486dxlv / ibm blue lightning cpu set- tings the amd 486dxlv and ibm blue li g htnin g cpus use the smiads# pin to indicate whether the y are currentl y executin g smm c y cles. these cpus g enerate addresses in the 6000h se g ment to access smm data. to preset operation for these cpus , pin 13 must be sensed low and pin 23 sensed hi g h at hardware reset time as described in section 3.3 "strap- selected interface options" . then , the re g ister bits must be set as follows. 1. set syscfg 5bh [ 7 ] = 0 to disable reroutin g of smi to irq15. 2. set syscfg 5bh [ 4 ] = 1 to confi g ure the smi# pin as bidirectional and define pin 136 as smiads#. 3. set syscfg 6bh [ 6 ] = 1 to enable pin 135 as smirdy#. 4. set syscfg a0h [ 2 ] = 1 to prevent sreset from occur- rin g within smm if desired. 5. set syscfg afh [ 7:4 ] to 7h for the cpu code se g ment smbase , which is 7000h on the 486dxlv and ibm cpus. when in smm , cpu accesses to the selected code se g ment will map to the dram at b000h. 6. set syscfg afh [ 3:0 ] to 6h for the cpu data se g ment smbase , which is 6000h on the 486dxlv and ibm cpus. when in smm , cpu accesses to the selected data se g ment will map to the dram at a000h. 7. finall y, set syscfg 30h [ 4 ] = 1 to enable the smm remappin g scheme. note that the amd 486dxlv and ibm blue li g htnin g pro- cessors j ump to the reset vector , fffffff0h , upon enterin g smm. syscfg 40h [ 7 ] ( refer to table 4-108 ) is provided for bios code to determine whether the j ump to this entr y point is due to an smi. proceed to the section 4.8.2 , "loading initial smm code and data" on pa g e 120. 82C465MV/mva/mvb opti ? pa g e 120 912-3000-016 revision: 3.0 4.8.1.4 non-smi cpu settings the irq15 smi select feature is provided for cpus without an smi pin to emulate smm throu g h irq15. for cpus with an smi , this feature must alwa y s be disabled. syscfg 5bh [ 7 ] = 0 does not reroute smis and allows the irq15 pin to function as normal. syscfg 5bh [ 7 ] = 1 enables smi to be internall y connected to irq15 and dis- ables the irq15 hardware pin function. therefore , an y enabled pmi events will tri gg er the internal irq15 si g nal. table 4-108 bios code jump bit 4.8.2 loading initial smm code and data on s y stem initialization , the s y stem mana g ement code and data se g ments must be loaded from rom with the appropri- ate information. this information will reside in the dram se g - ments at ph y sical startin g addresses a0000h and b0000h and , once loaded , will be write-protected except when the s y stem is operatin g in smm. step 1: system initialization (not in smm) on s y stem initialization , the bios must load initial code and data into the protected smm memor y space. normall y the s y stem will still be executin g out of rom at this point , but the memor y subs y stem is confi g ured and enabled. the d y namic smi relocation bit ( syscfg 31h [ 4 ], see table 4-109 ) is used for this purpose ( and for other reasons described in section 4.8.3 , "run-time smi address relocation" on pa g e 122 ) . syscfg 31h [ 4 ] is used as follows outside of smm. ? syscfg 31h [ 4 ] = 0: no relocation. this settin g prevents application software from accessin g smi memor y space. ? syscfg 31h [ 4 ] = 1: remap cpu addresses in the 3000/4000h se g ments to smi memor y space , the dram se g ments at b000h/a000h. this settin g provides the mechanism for initiall y loadin g smi code to the b000h/a000h re g ion. the bios sets syscfg 31h [ 4 ] = 1. it can then load code and data into dram se g ments b000h and a000h b y cop y in g it to se g ments 3000h and 4000h , respectivel y . even if the cpu in use defaults to different se g ments , such as cpus that use 6000h and 7000h , this first load operation must be addressed to the 3000h and 4000h se g ments. upon complet- in g the loadin g of all initial smm code and data , the bios clears syscfg 31h [ 4 ] to 0 to protect the smm space. step 2: software generation of smi havin g loaded the code and data , bios must now g enerate an smi to enter smm so that it can complete the smm initial- ization process ( b y chan g in g smbase if needed or perform- in g s y stem-specific tasks ) . to allow software smi g eneration to take place , syscfg 59h [ 7 ] must be written to 1. writin g syscfg 50h [ 7 ] = 1 then asserts smi to the cpu to start smm operation. writin g syscfg 50h [ 7 ] = 0 clears the smi. the smi routine must clear this bit; otherwise , smi re q uests will be g enerated continuousl y . table 4-110 shows these two re g ister bits. table 4-109 dynamic smi relocation bit 76543210 syscfg 40h pmu control register 1 default = 00h last j ump to reset vector: 0 = ads# 1 = smiads# 76543210 syscfg 31h control register 2 default = 40h d y namic smi relocation: 0 = normal 1 = remap 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 121 revision: 3.0 table 4-110 software smi enable registers step 3: reprogramming smbase once the s y stem has entered smm for the first time , the cpu smbase value can be repro g rammed for future use. the 82C465MV smbase value must be subse q uentl y updated to match the cpu smbase value. the operation should occur as follows. 1. smm code updates the smbase value of the cpu re g - ister save area. 2. smm code g enerates a resume instruction to return control to the bios initialization code. the new smbase value g ets written to the cpu re g isters. 3. bios code rewrites the 82C465MV smbase re g ister with the new value. usin g this procedure g uarantees reliable results. if the 82C465MV smbase re g ister is chan g ed from within smm , the chan g e takes place on the next code fetch or data access and ma y not operate predictabl y . 4.8.2.1 smbase register the smbase re g ister at syscfg afh operates in con j unc- tion with pro g ram option syscfg 5bh [ 4 ] . syscfg 5bh [ 4 ] selects the function of the smi# and smiads#/smiact# pins and also sets the base address of the smi code and data se g ments in the s y stem ( smbase ) . se g ments 3000h and 4000h are selected b y default; these map to b000h and a000h , respectivel y, when syscfg 5bh [ 4 ] = 0. other pro- cessors use se g ments 6000h and 7000h , which map to a000h and b000h , respectivel y when syscfg 5bh [ 4 ] = 1 ( note that the order of a000h and b000h chan g es in this case ) . the smbase re g ister provides independent relocation pro- g rammin g for the two se g ments associated with smi. the mappin g can be repro g rammed at an y time. after reset , as lon g as the new smbase re g ister is not written , the map- pin g uses the value associated with the syscfg 5bh [ 4 ] selection. once the smbase re g ister at syscfg afh has been written with an y value , all further mappin g is selected b y re g ister afh; chan g in g syscfg 5bh [ 4 ] could cause undesir- able results. table 4-111 smbase register 76543210 syscfg 59h pmu event register 2 default = 00h allow software smi: 0 = disable 1 = enable syscfg 50h pmu control register 5 default = 00h software start smi: 0 = clear smi 1 = start smi 76543210 syscfg afh smbase register default = 34h smm se g ment to be mapped to b000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 3h ) smm se g ment to be mapped to a000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 4h ) 82C465MV/mva/mvb opti ? pa g e 122 912-3000-016 revision: 3.0 4.8.3 run-time smi address relocation the d y namic smi relocation feature provides full memor y access control while in smm. smi relocation at run time is controlled b y syscfg 31h [ 4 ] . 4.8.3.1 relocation with standard interface smi the standard interface smi ( syscfg 5bh [ 4 ] = 0 ) uses the smiact# si g nal. normall y smm code , the data at memor y se g ments 3000h/4000h is not accessible b y the cpu because these addresses are mapped to the smi address space at b000h/a000h. however , syscfg 31h [ 4 ] can be used as follows to access this area durin g an smi routine. ? syscfg 31h [ 4 ] = 0: relocate all accesses in the 3000h/4000h se g ment to the b000h/a000h smi se g ment ( normal operation ) . ? syscfg 31h [ 4 ] = 1: code fetches ( cpu d/c# low ) from the cpu in the 3000h/4000h se g ment will be translated from the smi space at se g ment b000h/a000h. memor y data accesses ( cpu d/c# hi g h ) in the 3000h/4000h space will not be translated to smi space. this allows data in the 3000h/4000h memor y space to be accessed and saved to disk. 4.8.3.2 relocation with alternative interface smi the alternative mode smi ( syscfg 5bh [ 4 ] = 1 ) uses the smiads# si g nal. in this mode , syscfg 31h [ 4 ] must be pro- g rammed to 0 while in smm; settin g it to 1 is ille g al. for an smiads# c y cle , accesses in the 6000h/7000h se g ment are relocated to the a000h/b000h smi se g ment. for normal ads# c y cle , there is no relocation. table 4-112 shows the re g ister bits associated with smi address relocation. 4.8.4 smi event generation the re g isters shown below control the events that are allowed to g enerate an smi. the pro g rammin g occurs as fol- lows: 1. time-out , access , and interrupt events must be pro- g rammed to g enerate a pmi. 2. the pmi event must be enabled to g enerate the smi si g - nal. 3. smis are g loball y unmasked to allow full operation. this process is described in detail below. 4.8.4.1 time-out event generation of smi for time-out events , simpl y loadin g a non zero timer value and g eneratin g a dumm y access presets pmi g eneration on the next time-out. refer to section 4.7.2 , "timers" on pa g e 104 for information on pro g rammin g the timers. 4.8.4.2 access event generation of smi access events can be pro g rammed to g enerate an smi. the 82C465MV classifies accesses as current access or a next access dependin g on whether the timer associated with that access ran g e is still runnin g or has timed out , respectivel y . the available access event ran g es are defined in section 4.7.3 , "access events" on pa g e 107. ? next access - occurs after a time-out , the first time soft- ware attempts to access the i/o and/or memor y ran g e that caused the time-out. the next access feature provides a wa y for i/o accesses , to a peripheral whose timer has timed out , to cause an smi so that the peripheral can be powered up before the access takes place. next access can also speed up s y stem clocks if the s y stem is in hard- ware ( slow-clock ) doze mode when the access occurs. table 4-112 smi address relocation associated register bits ? current access - occurs an y time this feature is enabled for an i/o and/or memor y ran g e , whether or not the device has timed out. the current access pmi can be pro- g rammed to cause an smi , but cannot provide an y auto- matic means of controllin g s y stem clocks. 76543210 syscfg 31h control register 2 default = 40h d y namic smi relocation: 0 = normal 1 = remap syscfg 5bh pmu event register 4 default = 00h smi t y pe: 0 = intel 1 = other 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 123 revision: 3.0 if both the current access and next access features are enabled for an event , and the timer has timed out , an access will onl y cause a sin g le smi. since both access t y pes use the same pmi# , clearin g either one clears both events. table 4- 113 shows re g ister bits associated with current and next access g eneration. i/o blocking the i/o blockin g syscfg dbh [ 7 ] operates as follows. this selection allows the i/o access that causes a next access pmi to be either blocked ( if the peripheral is turned off , for example ) or passed throu g h. dbh [ 7 ] = 1 means the i/o will not be blocked; dbh [ 7 ] = 0 means the i/o on next access will be blocked and the cpu must be pro g rammed to restart the i/o command if desired. the feature defaults to blocked. note that if an i/o read access is blocked on g eneration of smi , a value of 0ffh is returned to the bus master. table 4-113 current and next access registers 4.8.4.3 no flush required on entry to smm the 82C465MVa part provides a feature that will allow the cpu smbase to be assi g ned to an address in the first 1mb of an y boundar y at or above 64mb ( i.e. , 64mb , 128mb , 192mb... ) . the cpu will reco g nize this re g ion as bein g out- side of cacheable memor y space and will not attempt to access its on-board cache to retrieve smm code and data. therefore , the cache need not be flushed on g eneration of the smiact# si g nal as occurs in the current 82C465MV desi g n. the feature works as in the followin g example with the associated re g ister bits shown in table 4-114. example the new cpu smbase address will be selected as 64mb + se g ment 3000h for code , se g ment 4000h for data , in this example. the addresses will map to 4030000h and 4040000h respectivel y . ?durin g non smi mode operations , the cpu will not g ener- ate the smiact# si g nal. therefore , the 82C465MV will not remap 3000h/4000h accesses to b000h/a000h. ? the first smi will take place to 30000h as usual and a cache flush will take place. durin g this first smi the cpu smbase can be modified to 4030000h; this value will be loaded to the cpu on execution of the resume instruction and will take effect on the next smi. also durin g the initial smi , smm code sets syscfg d3h [ 5 ] = 1 in the 82C465MVa re g isters to inhibit cache flush on entr y to smi. note: the smbase re g ister of the 82C465MV and 76543210 syscfg 5bh pmu event register 4 default = 00h gnr1 next access pmi#15: 0 = disable 1 = enable kbd next access pmi#14: 0 = disable 1 = enable dsk next access pmi#13: 0 = disable 1 = enable lcd next access pmi#12: 0 = disable 1 = enable syscfg dbh next access event generation register 2 default = 00h i/o blockin g control: 0 = block i/o next access 1 = unblock hdu_ access pmi#23 on next access? 0 = no 1 = yes com2_ access pmi#22 on next access? 0 = no 1 = yes com1_ access pmi#21 on next access? 0 = no 1 = yes gnr2_ access pmi#20 on next access? 0 = no 1 = yes syscfg deh current access event generation register default = 00h hdu_ access pmi#23 on current access? 0 = no 1 = yes com2_ access pmi#22 on current access? 0 = no 1 = yes com1_ access pmi#21 on current access? 0 = no 1 = yes gnr2_ access pmi#20 on current access? 0 = no 1 = yes gnr1_ access pmi#15 on current access? 0 = no 1 = yes kbd_ access pmi#14 on current access? 0 = no 1 = yes dsk_ access pmi#13 on current access? 0 = no 1 = yes lcd_ access pmi#12 on current access? 0 = no 1 = yes 82C465MV/mva/mvb opti ? pa g e 124 912-3000-016 revision: 3.0 82C465MVa parts must be written after the resume instruction from the initial smi , since it takes effect as soon as it is written. ?on subse q uent smis , the cpu will g enerate the new address with bit a26 hi g h to prevent it from attemptin g to access the code and data from its own internal cache. the 82C465MVa lo g ic will not see bit a26; however , it will see smiact# active and will infer that the current c y cle must come from protected smm dram , not the normal dram se g ment indicated. with the feature enabled , smm code has the additional choice of makin g dram data accesses either at the smbase dram se g ment or at the normal memor y se g ment for that address. syscfg d3h [ 7:6 ] are provided to select between the smm data se g ment and the normal data se g - ment for reads and writes , respectivel y . in this wa y, the movs instruction can be used b y smm code to cop y data between se g ments with no intermediate stora g e of the data. this feature is especiall y important if the 82C465MVa smbase is reassi g ned to select a000h for the data se g ment. syscfg d3h [ 7:6 ] could then be used to cop y data between the smm data se g ment and the video ram at a000h. table 4-114 smm flush control bits 4.8.4.4 interrupt event generation of smi as y nchronous events from peripheral devices re q uestin g ser- vice from the cpu are known as interrupt events. interrupts in this context include both the traditional at architecture irqs and additional inputs known as external power man- a g ement interrupts ( epmis ) . for the 82C465MV lo g ic , the desired interrupts are all g rouped into a sin g le event called intrgrp. intrgrp can then be enabled to cause an smi. if it is desired to g enerate an smi from the intrgrp event , settin g syscfg 57h [ 6 ] = 1 will allow an y of the selected interrupt events to g enerate pmi#6. once in the smi handler , the smm code can read the re g isters at syscfg 64h and a4h to determine which of the interrupt ( s ) caused the event. the irqs will remain latched for readin g in these re g isters until pmi#6 is cleared , at which time an y latched sources are cleared. the intrgrp irq select re g isters are shown below. 4.8.4.5 enabling of events to generate smi the re g isters listed below allow pmi events that are enabled to g enerate timer time-outs , accesses , and interrupts to cause smis. before settin g the smi event enable re g isters shown in table 4-116 , time-outs , accesses , and interrupts must be individuall y enabled to g enerate pmi events as fol- lows. ? for time-out events , loadin g a nonzero timer value and g eneratin g a dumm y access presets pmi g eneration on the next time-out. ? for current access events , the appropriate current access enable bit must be set to preset pmi g eneration on the followin g access. ? for next access events , the appropriate next access enable bit must be set. then , a valid time-out must take place to preset pmi g eneration on the followin g access. ? for interrupt events , the correspondin g intrgrp bit must be set and intrgrp must be enabled to g enerate pmi#6. then , pmi#6 will occur on an y enabled interrupt. the pmis should be enabled to g enerate smis throu g h the re g ister set below onl y after all desired pmi events have been enabled. settin g syscfg 5bh [ 6 ] = 1 then unmasks all the smis previousl y enabled. note that a resume event can be enabled to g enerate pmi#6. refer to the suspend and resume section for details on enablin g resume events. pmi#25 triggers the pmi#25 event is shared b y both epmi4 and the thermal mana g ement unit. syscfg d9h [ 3:2 ] enable smi for epmi4 onl y . syscfg dbh [ 6 ] enables smi onl y for cool-down clockin g entr y and exit. 76543210 syscfg d3h asym. dram select register default = 00h se g ment for smm data reads: 0 = a000h 1 = smbase ( syscfg afh [ 3:0 ]) (mva) se g ment for smm data writes: 0 = a000h 1 = smbase ( syscfg afh [ 3:0 ]) (mva) cache flush on smi entr y : 0 = enable 1 = disable (mva) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 125 revision: 3.0 table 4-115 intrgrp irq select registers 76543210 syscfg 57h pmu control register 6 default = 00h intrgrp g en- erates pmi#6: 0 = disable 1 = enable syscfg 64h intrgrp irq select register 1 default = 00h irq14: 0 = disable 1 = enable irq8: 0 = disable 1 = enable irq7: 0 = disable 1 = enable irq6: 0 = disable 1 = enable irq5: 0 = disable 1 = enable irq4: 0 = disable 1 = enable irq3: 0 = disable 1 = enable irq1: 0 = disable 1 = enable syscfg a4h intrgrp irq select register 2 default = 00h irq15: 0 = disable 1 = enable irq13: 0 = disable 1 = enable irq12: 0 = disable 1 = enable irq11: 0 = disable 1 = enable irq10: 0 = disable 1 = enable irq9: 0 = disable 1 = enable irq0: 0 = disable 1 = enable table 4-116 smi event enable registers 76543210 syscfg 58h pmu event register 1 default = 00h lowbat pmi#3 smi: 00 = disable 11 = enable epmi2 pmi#2 smi: 00 = disable 11 = enable epmi1 pmi#1 smi: 00 = disable 11 = enable llowbat pmi#0 smi: 00 = disable 11 = enable syscfg 59h pmu event register 2 default = 00h resume intrgrp pmi#6, suspend pmi#7 smi: 00 = disable 11 = enable r_timer pmi#5 smi: 00 = disable 11 = enable idle_timer pmi#4 smi: 00 = disable 11 = enable syscfg 5ah pmu event register 3 default = 00h gnr1_timer pmi#11 smi: 00 = disable 11 = enable kbd_timer pmi#10 smi: 00 = disable 11 = enable dsk_timer pmi#9 smi: 00 = disable 11 = enable lcd_timer pmi#8 smi: 00 = disable 11 = enable syscfg 5bh pmu event register 4 default = 00h global smi control: 0 = allow 1 = mask syscfg d8h pmu event register 5 default = 00h hdu_timer pmi#19 hdu_access pmi#23 smi: 00 = disable 11 = enable com2_timer pmi#18 com2_access pmi#22 smi: 00 = disable 11 = enable com1_timer pmi#17 com1_access pmi#21 smi: 00 = disable 11 = enable gnr2_timer pmi#16 gnr2_access pmi#20 smi: 00 = disable 11 = enable syscfg d9h pmu event register 6 default = 00h 82C465MV/mva/mvb opti ? pa g e 126 912-3000-016 revision: 3.0 4.8.5 drq generation of smi the 82C465MVa allows activit y on the drq pins to g enerate an smi. the smi takes place before the dma transfer occurs , allowin g smm code to emulate or modif y the operation. writ- in g the bit to clear the pmi then allows an y pendin g dma operation to take place immediatel y . there are certain latenc y limitations for dma operations. for example , flopp y disk dma transfers g enerall y must be ser- viced within 14 s from receipt of drq2 in order to avoid an overrun condition. entr y into smm re q uires a considerable amount of time in itself. therefore , smm routines that trap dma accesses must be structured concisel y so that the dma c y cle is allowed to occur before the latenc y limit is exceeded. table 4-117 dma trap related bits 4.8.6 servicing an smi the re g ister set shown in table 4-118 is used b y smm code to enable s y stem events to cause smis , to determine the events that caused an active smi , and to clear the events. upon entr y to smm , the chip clears the smi# si g nal to the cpu. then , determinin g the source of the smi is a simple procedure. 1. read the re g isters at syscfg 5ch , 5dh , dch , and ddh. an y nonzero bits indicate pmi sources. more than one can be active. 2. the pmi number will indicate the source of the service re q uest. in case pmi#6 is indicated , also read syscfg 64h and a4h ( described earlier in section 4.8.4.4 , "inter- rupt event generation of smi" on pa g e 124 ) to deter- mine which irq line was responsible for the event. 3. service the events in the order desired. upon completion of each service , write a '1' back to the event source re g - ister bit to clear that event. continue in this manner until all events are serviced and all the smi service re g isters are clear. 4. issue the proper cpu instruction to return from smm operation. ri pmi#26 smi: 00 = disable 11 = enable epmi4 pmi#25 smi: 00 = disable 11 = enable epmi3 pmi#24 smi: 00 = disable 11 = enable syscfg dbh next access event generation register 2 default = 00h smi on cool- down clockin g entr y /exit pmi#25 smi: 0 = disable 1 = enable table 4-116 smi event enable registers (cont.) 76543210 76543210 syscfg d6h pmu control register 10 default = 00h dma trap pmi#28 smi: 0 = disable 1 = enable (mva) syscfg ddh pmu smi source register 4 default = 00h pmi#28, dma: 0 = clear 1 = active (mva) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 127 revision: 3.0 if an y events are still pendin g upon resume from smm , the 82C465MV chip will issue a new smi# immediatel y . 4.8.6.1 pmi source register details re g isters 5ch , 5dh , dch , and ddh indicate the smi source. when a pmi event occurs , the correspondin g bit will be set to '1' and the smi# si g nal will then be g enerated. in the smi ser- vice routine , smm code must check these re g isters for the pmi source ( s ) and then clear them. otherwise , for all but the epmi pins the latched pmi source will g enerate smi# contin- uousl y . smi code normall y clears onl y one event at a time to keep track of the events as the y are serviced , but all events can be cleared at once if desired. note that clearin g bit 5ch [ 6 ] will clear bit 5ch [ 7 ] also. refer to the suspend and resume section of this document for information on pmi#6 when it is used to indicate a resume event. table 4-118 smi service registers 4.8.6.2 epmi pin pmi sources the epmi1-2 pin pmi source indicator bits behave a little dif- ferentl y than the rest of the pmi source indicator bits. for pmis #1 and #2 , the epmi1-2 inputs are not latched b y default , so syscfg 5ch [ 2:1 ] are not latched. therefore , an external device could tri gg er an smi b y to gg lin g one of the epmi1-2 lines , but if the device returns the epmi line to its inactive state before smm code reads syscfg 5ch [ 2:1 ], the code would not be able to reco g nize the event that tri gg ered the smi. likewise , an epmi1-2 ed g e could initiate a resume from suspend mode , but then would not be reco g nized if the epmi pin went to its inactive state. syscfg a1h [ 0 ] is provided to allow epmi1-2 to be latched like other pmis. if syscfg a1h [ 0 ] is written to 1 , epmi1-2 events will be latched at syscfg 5ch [ 2:1 ] . writin g a '1' into the active bit ( s ) then clears the pmi. for pmis #24 and #25 , the epmi3-4 inputs are alwa y s latched , re g ardless of syscfg a1h [ 0 ] settin g . 76543210 syscfg 5ch pmi source register 1 (write 1 to clear) default = 00h pmi#7, suspend: 0 = inactive 1 = active pmi#6, resume or intrgrp: 0 = inactive 1 = active pmi#5, r_timer time-out: 0 = inactive 1 = active pmi#4, idle_tmr time-out: 0 = inactive 1 = active pmi#3, lowbat: 0 = inactive 1 = active pmi#2, epmi2: 0 = inactive 1 = active pmi#1, epmi1: 0 = inactive 1 = active pmi#0, llowbat: 0 = inactive 1 = active syscfg 5dh pmi source register 2 (write 1 to clear) default = 00h pmi#15, gnr1_ access: 0 = inactive 1 = active pmi#14, kbd_access: 0 = inactive 1 = active pmi#13, dsk_access: 0 = inactive 1 = active pmi#12, lcd_access: 0 = inactive 1 = active pmi#11, gnr1_timer: 0 = inactive 1 = active pmi#10, kbd_timer: 0 = inactive 1 = active pmi#9, dsk_timer: 0 = inactive 1 = active pmi#8, lcd_timer: 0 = inactive 1 = active syscfg dch pmu smi source register 3 (write 1 to clear) default = 00h pmi#23, hdu_ access: 0 = inactive 1 = active pmi#22, com2_ access: 0 = inactive 1 = active pmi#21, com1_ access: 0 = inactive 1 = active pmi#20, gnr2_ access: 0 = inactive 1 = active pmi#19, hdu_ timer: 0 = inactive 1 = active pmi#18, com2_ timer: 0 = inactive 1 = active pmi#17, com1_ timer: 0 = inactive 1 = active pmi#16, gnr2_ timer: 0 = inactive 1 = active syscfg ddh pmu smi source register 4 default = 00h reserved pmi#28, dma: 0 = clear 1 = active (mva) pmi#27, doze_timer: 0 = clear 1 = active pmi#26, ri: 0 = clear 1 = active pmi#25, epmi4 pin/ cool-down clockin g : 0 = clear 1 = active pmi#24, epmi3 pin: 0 = clear 1 = active 82C465MV/mva/mvb opti ? pa g e 128 912-3000-016 revision: 3.0 4.8.6.3 i/o smi trap indication the 82C465MVa part provides a means for smm code to determine the i/o port whose access caused the smi , as well as a bit to indicate whether the access was a read or a write access. table 4-119 i/o access trap registers 4.8.6.4 utility registers the re g isters below provide a g eneral purpose stora g e re g ion and a means of g eneratin g warnin g beeps on the s y s- tem speaker without modif y in g the at-compatible i/o ports. table 4-120 utility registers 76543210 syscfg d6h pmu control register 10 default = 00h i/o port access trapped ( ro ) : 0 = i/o read 1 = i/o write (mva) access trap bit a9 ( ro ) (mva) access trap bit a8 ( ro ) (mva) syscfg d7h access port address register default = 00h access trap address bits a [ 7:0 ] : - these bits, alon g with a [ 9:8 ] in bits d6h [ 1:0 ] , provide the 10-bit i/o address of the port access that caused the smi trap. syscfg d6h [ 2 ] indicates whether an i/o read or i/o write access was trapped. (mva) 76543210 syscfg 52h scratchpad register 1 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: data phase information, low b y te (mvb) syscfg 53h scratchpad register 2 default = 00h general purpose stora g e b y te - for cisa confi g uration c y cles: data phase information, hi g h b y te (mvb) syscfg 6ch scratchpad register 3 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, low b y te (mvb) syscfg 6dh scratchpad register 4 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, hi g h b y te (mvb) syscfg 6eh scratchpad register 5 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, low b y te (mvb) syscfg 6fh scratchpad register 6 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, hi g h b y te (mvb) syscfg 51h beeper control register default = 00h general purpose stora g e bits beeper control: 00 = no action 10 = off 01 = 1khz 11 = 2khz 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 129 revision: 3.0 4.9 system power management the power mana g ement unit lo g ic provides two hardware means of controllin g the cpu clock speed. doze mode hardware causes the cpu speed to slow down or stop to save power when there is no si g nificant activit y . thermal management hardware forces the cpu speed to be reduced to avoid overheatin g the cpu when the s y stem is runnin g at full speed for too lon g . both of these mechanisms en g a g e the stop clock mechanism to slow down the cpu. 4.9.1 stpclk# mechanism to change cpu speed man y cpus contain a phase-locked loop ( pll ) fre q uenc y g enerator that takes the external clock fre q uenc y input and doubles or triples it. an y cpu that depends on an internal pll for its fre q uenc y g eneration re q uires an input to allow it to stop operations in an orderl y manner and in a known state until a new fre q uenc y can be established and locked onto. this t y pe of cpu is referred to as a pll-based cpu , as opposed to a static cpu whose clock can be chan g ed at an y time. static cpus usuall y ( but not alwa y s ) re q uire a 2x clock input , while pll-based cpus almost alwa y s use a 1x clock input. the cpu speed control input is called the stop clock pin ( stpclk# ) . the name is misleadin g, since the stop clock protocol must be followed even when switchin g between clock speeds , not j ust when stoppin g the clock alto g ether. however , the 82C465MV interface uses this same name for clarit y . the stpclk# mechanism is needed as follows. ? static cpus ma y or ma y not have a stop re q uest input pin. in either case , the cpu can be sped up , slowed down , or stopped at an y time. no protocol is re q uired for doze mode on this t y pe of cpu , but if it does have a stop clock input the stpclk# feature should be activated to save additional power. ? pll-based cpus re q uire a stop re q uest si g nal from the power mana g ement unit re q uestin g the cpu to stop all operations and disconnect from its clock input so that the clock can be chan g ed or stopped. this si g nal is called stpclk# , susp# , dfsreq# , or similar. ? pll-based cpus also must tell the 82C465MV when the y are actuall y read y to allow the clock to be stopped or chan g ed. some cpus g enerate a special bus c y cle to indi- cate this state; when the y receive rdy# from the chipset the y will g o to their stop g rant state. other cpus have a dedicated pin to indicate this condition to the chipset , called stpgnt# , suspa# , dfsrdy# , or similar. in addition to usin g a stpclk# mechanism to chan g e speed , most cpus provide a clock-stoppin g feature that allows the cpuclk input to be completel y stopped durin g periods of no activit y . a s y stem interrupt , such as initiated b y a ke y stroke or a timer interrupt , can cause the 82C465MV to restart the cpu almost immediatel y . stoppin g the cpu clock is usuall y initiated b y software ( apm for example ), but could also be initiated b y the hardware doze mechanism. 4.9.1.1 hardware considerations to enable the stpclk# re q uest lo g ic of the 82C465MV , the lo g ic must sample pins 13 and 23 hi g h at reset. these pins must be strapped hi g h with 10k w resistors. refer to section 3.3 , "strap-selected interface options" on pa g e 5 for com- plete details. 4.9.1.2 programming to enable stpclk# operation , the re g isters shown below must be pro g rammed as follows. ? syscfg 65h [ 6 ] and 66h [ 5 ] are set accordin g to the slowed or stopped cpu clock desired: -for completel y stoppin g the cpu clock: set syscfg 65h [ 6 ] = 1 for latched stpclk# operation and syscfg 66h [ 5 ] = 1 for stoppin g the cpu clock durin g doze mode. - for slowin g down the cpu clock: set syscfg 65h [ 6 ] = 0 for pulsed stpclk# operation and syscfg 66h [ 5 ] = 0 for slowin g the cpu clock durin g doze mode ( the slowdown speed is set in syscfg 41h [ 4:2 ] as described later ) . ? enable the stpclk# lo g ic mechanism b y settin g syscfg 61h [ 2 ] = 1 for an y cpu that re q uires a clock chan g e re q uest si g nal ( stpclk# , dfsreq# , susp# ) to chan g e operatin g fre q uenc y . even for static cpus whose fre q uenc y can be chan g ed d y namicall y, if a stpclk# input is provided it should be used to save power. the additional power savin g s is substantial , especiall y in soft- ware doze mode when the cpu clock is stopped. ? if stpclk# is used , enable the stop g rant protocol as needed. almost all 1x cpus re q uire settin g syscfg 66h [ 0 ] = 1 to reco g nize the stop g rant c y cle. in addition: - cpus that have a stop g rant pin ( stpgnt# , dfs- rdy# , suspa# ) re q uire settin g syscfg 66h [ 3 ] = 1 and syscfg 57h [ 3 ] = 0 to enable the 82C465MV stpgnt# input on pio3. - for cpus that do not have a stop g rant pin , the stpgnt# input function to the 82C465MV be disabled ( syscfg 66h [ 3 ] = 0 ) . otherwise , the chipset ma y pre- maturel y detect a stop g ranted condition and will chan g e the clock unconditionall y, likel y han g in g the cpu. 82C465MV/mva/mvb opti ? pa g e 130 912-3000-016 revision: 3.0 ? enable and set a switchin g dela y throu g h syscfg b0h [ 7:0 ] to select the precise minimum switchin g dela y re q uired for the cpu in use. if disablin g the stpclk# si g - nal , set syscfg b0h [ 7:0 ] = 0 for no dela y . the stpclk# se q uence will now be observed an y time the hardware doze feature chan g es the clock speed , or when apm commands the clock to stop. for example , durin g an apm stop clock operation the 82C465MV: 1. asserts its stpclk# output 2. waits for either a stop g rant c y cle or a stpgnt# si g nal 3. returns rdy# to the cpu 4. stops the clock to the cpu 5. awaits a restart event such as an interrupt 6. restarts the clock to the cpu 7. waits for the switchin g dela y time pro g rammed 8. de-asserts its stpclk# output and continues operation. the se q uence for slowin g the clock is similar except that instead of steps 4 throu g h 6 above , the 82C465MV simpl y switches the clock speed. the re g isters associated with the clock speed chan g e mech- anism are shown in table 4-121. additional detailed descrip- tive information follows the re g ister bit listin g s. table 4-121 register bits associated with stpclk# feature 76543210 syscfg 57h pmu control register 6 default = 00h pio3 direction: 0 = input 1 = output syscfg 61h debounce register default = 00h stpclk# si g nal: 0 = disable 1 = enable syscfg 65h doze register default = 00h stpclk# control: 0 = pulse 1 = latch syscfg 66h pmu control register 8 default = 00h doze t y pe: 0 = slow cpu clock 1 = stop cpu clock pin 171 function: 0 = pio3 1 = stpgnt# cpu clock chan g e proto- col re q uired? 0 = no 1 = yes syscfg b0h stop clock delay register default = 00h stop clock dela y : 0 = disable 1 = enable stop clock dela y time base: 0 = 32khz/4 ( ~122 us ) 1 = fbclk/4 dela y count: - this value multiplies the time base period selected in bit [ 6 ] . there is an additional 6 fbclk dela y for all selections, even no dela y . sample approximate dela y s based on 32khz/25mhz selections: 000000 = no dela y 000011 = 366 s/480ns 001001 = 1.1ms/1.44 s 000001 = 122us/160ns ... ... 000010 = 244 s/320ns 001000 = 976 s/1.28 s 111111 = 7.7ms/10.0 s 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 131 revision: 3.0 stpclk# pulse/latch control the stpclk# pulse/latch control bit , syscfg 65h [ 6 ], is meanin g ful onl y if the stpclk# protocol is enabled b y syscfg 61h [ 2 ] = 1 and syscfg 66h [ 0 ] = 1. the mecha- nism operates as follows. ? when stpclk# is set to pulse for chan g in g the fre- q uenc y of the cpu clock ( slowed cpuclk mode ), syscfg b0h [ 6:0 ] determine the duration of the pulse startin g from the rdy# respondin g to the cpu stop g rant c y cle and endin g with stpclk# g oin g inactive. the 82C465MV lo g ic chan g es the clock speed j ust after g ener- atin g rdy# to the cpu. ? when stpclk# is set to latch for stoppin g the cpu clock ( stopped cpuclk mode ), stpclk# g oes low and sta y s low. just after g eneratin g the rdy# respondin g to the cpu stop g rant c y cle , the lo g ic slows down and then stops the clock. upon an y enabled doze reset event , the 82C465MV lo g ic restarts the clocks at doze speed , then brin g s them to full operatin g speed. syscfg b0h [ 6:0 ] determine the start-up dela y between the clocks returnin g to full speed and the stpclk# si g nal g oin g inactive. the total time stpclk# is active must also include the time from when the 82C465MV lo g ic sets it active to the point where the cpu responds with a stop g rant c y cle , which is cpu-dependent. stop clock delay selections most currentl y available cpus specif y a dela y of 1ms from cpuclk stable operation to stpclk g oin g inactive. to anticipate future cpus that ma y re q uire a clock stabilization dela y time si g nificantl y g reater or less than 1ms , the 82C465MV provides a re g ister to offer total dela y flexibilit y . the stop clock dela y time base bit , syscfgb0h [ 6 ], provides two ran g es: 32khz/4 ( for a 122 s period ), and oscclk/4 ( for a 200ns period @ 20mhz , for example ) . note that when usin g the oscclk dela y ran g e , the values are calculated on the effective input fre q uenc y . if a 2x osc- clk is used , it will be divided b y 2 for an effective 1x input clock. in other words , if the input clock is 2x , the dela y period becomes oscclk/8 to compensate. also note that re g ardless of dela y settin g, even for no dela y, there will alwa y s be an additional six cpuclks of dela y over an y settin g ( whether based on cpuclk or 32khz ) . the lo g ic re q uires this time to en g a g e its se q uencer. 4.9.2 doze mode the 82C465MV power mana g ement unit includes doze mode control lo g ic. doze is the state in which the cpu and the 82C465MV chipset are full y alive and operational , y et runnin g at a speed that is g reatl y reduced in order to save power. the 82C465MV en g a g es doze mode when it sees no activit y in certain pre-definable areas for a certain time period. once initialized b y software , the process is com- pletel y controlled b y hardware. no further software interven- tion is needed , but an smi can be g enerated if desired. even thou g h doze mode is intended to operate indepen- dentl y without application or bios intervention , the 82C465MV provides lo g ic hooks to software for software- based power control. the most common t y pe of software- based power control follows the microsoft? advanced power mana g ement ( apm ) specification , which allows applications to inform the operatin g s y stem when the y are idle or do not re q uire full processin g power. the operatin g s y stem , in turn , makes bios calls that can do an y of the followin g : ? turn off or put into a standb y mode an y unneeded periph- erals ?slow s y stem clock speeds ? turn off clocks to the cpu. therefore , the 82C465MV doze mode lo g ic provides for three doze mode operations: hardware-controlled slowdown , software-controlled slowdown , and software-controlled slow- down with a stopped cpu clock. the three modes are ver y similar and are outlined in the sec- tions below , followed b y descriptions of re g isters that the three modes have in common. note , however , that the hard- ware mechanism of clock slowin g or stoppin g is dependent on the t y pe of cpu in use. the 82C465MV provides the stop clock lo g ic described below. 4.9.2.1 dual doze timer reload selections the standard 82C465MV part can g enerate a doze timer time-out in as little as 2ms. however , this selection is not compatible with all applications. for example , stable operat- in g speed mi g ht be desirable for at least 2s after a ke y board interrupt in order to completel y service the event and prevent dela y s on subse q uent ke y strokes. another operation , such as video access , mi g ht allow a return to doze mode almost immediatel y . therefore , the 82C465MVa part provides a choice of two time-out timers for each device. when an interrupt for the device or access in the ran g e associated with that device occurs , the event tri gg ers a doze reset that reloads the selected timer for that device with the time-out value associ- ated with that timer. onl y when both timers have expired will the s y stem return to doze mode operation. on the ori g inal 82C465MV part , com port , lpt port , and gnr accesses could not cause a doze reset. on the 82C465MVa version , these accesses can be pro g rammed to enable a doze reset. however , to maintain backward com- patibilit y with the 82C465MV and 82c463mv , the com1 , com2 , lpt , and gnr accesses point to the secondar y doze timer at reset; this timer in turn is pro g rammed for no dela y at reset. the doze lo g ic interprets the no dela y settin g as inhibitin g doze reset for that source. 82C465MV/mva/mvb opti ? pa g e 132 912-3000-016 revision: 3.0 the smi , epmi1 , and intr si g nals are also potential sources of doze reset. however , these si g nals alwa y s use doze time- out 0 and cannot select doze time-out 1. re g ardin g smi g eneration on doze events: doze time-out events on doze_0 and doze_1 can be individuall y pro- g rammed to g enerate an smi throu g h syscfg d9h [ 7:6 ], which are redefined on the 82C465MVa part to select the time-out ( s ) that will cause an smi. doze reset events are all individuall y pro g rammable to g enerate smis. table 4-122 doze time-out control registers 76543210 syscfg 76h doze reload select register 1 default = 00h lcd_access: 0 = doze_0 1 = doze_1 (mva) kbd_access: 0 = doze_0 1 = doze_1 (mva) dsk_access: 0 = doze_0 1 = doze_1 (mva) hdu_access: 0 = doze_0 1 = doze_1 (mva) com1&2_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) lpt_access: 0 = doze_0 1 = doze_1 default = 1 (mva) gnr1_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) gnr2_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) syscfg 77h doze reload select register 2 default = 00h irq8: 0 = doze_0 1 = doze_1 (mva) irq7: 0 = doze_0 1 = doze_1 (mva) irq6: 0 = doze_0 1 = doze_1 (mva) irq5: 0 = doze_0 1 = doze_1 (mva) irq4: 0 = doze_0 1 = doze_1 (mva) irq3: 0 = doze_0 1 = doze_1 (mva) irq1: 0 = doze_0 1 = doze_1 (mva) irq0: 0 = doze_0 1 = doze_1 (mva) syscfg 78h doze reload select register 3 default = 00h ldev#: 0 = doze_0 1 = doze_1 (mva) irq15: 0 = doze_0 1 = doze_1 (mva) irq14: 0 = doze_0 1 = doze_1 (mva) irq13: 0 = doze_0 1 = doze_1 (mva) irq12: 0 = doze_0 1 = doze_1 (mva) irq11: 0 = doze_0 1 = doze_1 (mva) irq10: 0 = doze_0 1 = doze_1 (mva) irq9: 0 = doze_0 1 = doze_1 (mva) syscfg d9h pmu event register 6 default = 00h doze_timer pmi#27 smi: 00 = disable 01 = enable doze_0 (mva) 10 = enable doze_1 (mva) 11 = enable both syscfg 41h pmu control register 2 default = 00h doze_0 time-out select: 000 = 2 ms 100 = 128 ms 001 = 4 ms 101 = 512ms 010 = 8 ms 110 = 2s 011 = 32 ms 111 = 8s syscfg 79h pmu control register 11 default = 00h doze_1 time-out select (mva) : 000 = no dela y ( default ) 100 = 64ms 001 = 1ms 101 = 256 ms 010 = 4ms 110 = 1s 011 = 16ms 111 = 4s 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 133 revision: 3.0 4.9.2.2 presetting events to reset doze mode before enablin g doze mode operation , whether hardware or software doze mode , some preparation must be made for the event or events that will reset doze mode and brin g the s y s- tem back to full operation. otherwise , especiall y in the case of apm stop clock mode , there would be no wa y to execute cpu instructions to restart the cpu clock. therefore , it is first necessar y to choose the source or sources that will perform a doze reset. doze reset will , if the s y stem is currentl y in doze mode , restore the s y stem clocks to full operatin g speed. doze reset also reloads the doze_timer with its ori g inal pro g rammed value. ? settin g syscfg 41h [ 1 ] = 1 enables lcd_access , kbd_access , dsk_access , and hdu_access to reset doze mode and reload the doze_timer. if the doze_timer has timed out and switched operation to doze speed , this reload will chan g e the s y stem clocks back to their normal speed. obviousl y, this bit has no effect if stopped ( not j ust slowed ) cpuclk operation is pro g rammed. ? syscfg 65h [ 5 ] selects the epmi1 pin as a doze reset tri gg er ( level-tri gg ered ) . ? syscfg 62h [ 7:0 ], a2h [ 5:0 ], and 65h [ 3 ] define individual irqs that can tri gg er a doze reset. ? syscfg 65h [ 7 ] allows all enabled interrupts ( i.e. , an y event that to gg les the intr si g nal to the cpu ) to reset doze mode. once the doze mode reset events have been pro g rammed ( see table 4-123 ), either hardware or software doze mode can be enabled as described in the followin g sections. table 4-123 register bits that select doze mode reset events 76543210 syscfg 41h pmu control register 2 default = 00h lcd, dsk, kbd, hdu _access events reset doze mode: 0 = disable 1 = enable syscfg 62h irq doze register 1 (wo) default = 00h irq13 doze reset: 0 = disable 1 = enable irq8 doze reset: 0 = disable 1 = enable irq7 doze reset: 0 = disable 1 = enable irq12 doze reset: 0 = disable 1 = enable irq5 doze reset: 0 = disable 1 = enable irq4 doze reset: 0 = disable 1 = enable irq3 doze reset: 0 = disable 1 = enable irq0 doze reset: 0 = disable 1 = enable syscfg a2h irq doze register 2 (wo) default = 00h irq15 doze reset: 0 = disable 1 = enable irq14 doze reset: 0 = disable 1 = enable irq11 doze reset: 0= disable 1= enable irq10 doze reset: 0 = disable 1 = enable irq9 doze reset: 0 = disable 1 = enable irq6 doze reset: 0 = disable 1 = enable syscfg 65h doze register default = 00h all interrupts to cpu reset doze mode: 0 = disable 1 = enable epmi1 doze reset: 0 = disable 1 = enable smi resets doze mode? 0 = no 1 = yes irq1 doze reset: 0 = disable 1 = enable 82C465MV/mva/mvb opti ? pa g e 134 912-3000-016 revision: 3.0 4.9.2.3 ldev# doze reset activit y on the local bus can reset doze mode and cause a return to full operatin g speed. the 82C465MVa lo g ic pro- vides two bits to enable doze reset separatel y for local bus i/o accesses and local bus memor y accesses. the doze reset is tri gg ered b y ldev# g oin g active and is q ualified b y the m/io# si g nal. 4.9.2.4 doze reset inside smm the 82C465MVa part allows an smi to reset doze mode if the clock is stopped from within s y stem mana g ement mode. syscfg 65h [ 4 ] in the 82C465MV part enables doze mode reset when the smi si g nal g oes active , but since smi is masked on entr y to smm , an smi tri gg ered while the s y stem is in smm is not seen until some other tri gg er resets doze mode. settin g syscfg 79h [ 4 ] = 1 handles doze reset onl y from within smm. set syscfg 65h [ 4 ] = 1 to handle smi doze mode exit from outside of smm. table 4-125 shows the two bits. table 4-124 local bus doze reset registers table 4-125 doze reset bits inside and outside of smm 76543210 syscfg a2h irq doze register 2 (wo) default = 00h local bus i/o access doze reset: 0 = disable 1 = enable (mva) local bus mem- or y access doze reset: 0 = disable 1 = enable (mva) syscfg 78h doze reload select register 3 default = 00h ldev#: 0 = doze_0 1 = doze_1 (mva) 76543210 syscfg 79h pmu control register 11 default = 00h smi resets doze mode if clock is stopped inside smm? 0 = no 1 = yes (mva) syscfg 65h doze register default = 00h smi resets doze mode? 0 = no 1 = yes 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 135 revision: 3.0 4.9.2.5 automatic (hardware) doze mode the chipset can be set up for hardware-controlled slowdown doze mode b y pro g rammin g the followin g information. 1. set up the hardware and pro g rammin g to consider the stop clock mechanism as described in section 4.9.1 , "stpclk# mechanism to change cpu speed" on pa g e 129. 2. pro g ram the events that will reset doze mode as described in section 4.9.2.2 , "presetting events to reset doze mode" on pa g e 133. 3. select the time-out , that is , the time re q uired after the last event before the s y stem can be considered inac- tive , in syscfg 41h [ 7:5 ] . a two second time-out is t y pi- cal. 4. select the clock divisor from syscfg 41h [ 4:2 ] . when choosin g a divisor , keep in mind that most cpus cannot run below 8mhz , while the limit for clock-tripled cpus is usuall y 12.5mhz. 5. set syscfg 66h [ 5 ] = 0 for slow-clock mode as opposed to stop-clock mode. 6. set syscfg 65h [ 4 ] = 1 if chipset should exit doze mode for smis , or = 0 if the smis can run ade q uatel y at the doze speed. note that since the clock chan g e dela y is t y picall y 1ms , it ma y be practical to simpl y run the smi code at the slower speed. 7. finall y, enable the hardware doze_timer b y settin g syscfg 41h [ 0 ] = 0. after the selected period of inactivit y, the cpu clock and the chipset clock will automaticall y be set to a low-speed mode. on the event of an y of the enabled accesses , smis , or irqs , the clock will a g ain speed up for full y active operation. table 4-126 shows the above discussed re g ister bits. table 4-126 hardware doze mode registers 76543210 syscfg 41h pmu control register 2 default = 00h doze_0 time-out select: 000 = 2 ms 100 = 128 ms 001 = 4 ms 101 = 512ms 010 = 8 ms 110 = 2s 011 = 32 ms 111 = 8s doze mode s y stem clock speed: 000 = oscclk/1 100 = oscclk/16 001 = oscclk/2 101 = oscclk/3 010 = oscclk/4 110 = reserved 011 = oscclk/8 111 = reserved doze control select: 0 = hardware 1 = software syscfg 66h pmu control register 8 default = 00h doze t y pe: 0 = slow cpu clock 1 = stop cpu clock syscfg 65h doze register default = 00h smi resets doze mode? 0 = no 1 = yes syscfg 50h pmu control register 5 default = 00h write: 1 to start doze read: doze status 0 = countin g 1 = timed out 82C465MV/mva/mvb opti ? pa g e 136 912-3000-016 revision: 3.0 4.9.2.6 apm (software) doze mode the chipset can be set up for software-initiated , slowed or stopped cpuclk doze mode in a ver y strai g htforward man- ner. 1. set up the hardware and pro g rammin g to consider the stop clock mechanism as described in section 4.9.1 , "stpclk# mechanism to change cpu speed" on pa g e 129. 2. pro g ram the events that will reset doze mode as described in section 4.9.2.2 , "presetting events to reset doze mode" on pa g e 133. 3. set syscfg 65h [ 4 ] = 1 if chipset should exit doze mode for smis , or = 0 if the smis can run ade q uatel y at the doze speed. syscfg 65h [ 4 ] must be set to 1 for stop clock operation or else the smi will be missed alto g ether. 4. select the clock divisor from syscfg 41h [ 4:2 ] . when choosin g a divisor , keep in mind that most cpus cannot run below 8mhz , while the limit for clock-tripled cpus is usuall y 12.5mhz. if the cpu clock will be stopped , i g nore the lower cpu limit and use a ver y low clock speed to save power to the chipset ( whose clock is also slowed ) . 5. disable the hardware doze_timer b y settin g syscfg 41h [ 0 ] = 1. at this point the s y stem is read y for apm control. when apm makes a call for low or ver y low power operation , the bios or power mana g ement code simpl y : ? for slow clock doze: sets syscfg 65h [ 6 ] = 0 and syscfg 66h [ 5 ] = 0 -- or -- for stop clock doze: sets syscfg 65h [ 6 ] = 1 and syscfg 66h [ 5 ] = 1 ? sets syscfg 50h [ 3 ] = 1 to initiate the doze mode. on the event of an y of the enabled accesses , smis , or irqs , the clock will a g ain speed up for full y active operation. table 4-127 software doze mode registers 76543210 syscfg 41h pmu control register 2 default = 00h doze mode s y stem clock speed: 000 = oscclk/1 100 = oscclk/16 001 = oscclk/2 101 = oscclk/3 010 = oscclk/4 110 = reserved 011 = oscclk/8 111 = reserved doze control select: 0 = hardware 1 = software syscfg 66h pmu control register 8 default = 00h doze t y pe: 0 = slow cpu clock 1 = stop cpu clock syscfg 65h doze register default = 00h smi resets doze mode? 0 = no 1 = yes syscfg 50h pmu control register 5 default = 00h write: 1 to start doze read: doze status 0 = countin g 1 = timed out 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 137 revision: 3.0 4.9.2.7 start doze bit syscfg 50h [ 3 ] serves two purposes: to start doze mode and to read the doze_timer status. ? write: start apm doze mode '1' = start doze mode ( if syscfg 40h [ 0 ] = 1 ) '0' = no effect ? read: hardware doze_timer time-out status bit '1' = hardware doze_timer has timed out '0' = hardware doze_timer still countin g 4.9.2.8 using doze time-out to trigger an smi in addition to the abilit y to reset doze mode when an smi is encountered , the 82C465MV has the abilit y to g enerate pmi#27 when the doze_timer times out. settin g syscfg d9h [ 7:6 ] = 11 enables the pmi to g enerate an smi ( see table 4-128 ) . table 4-128 doze_timer smi generation bits 76543210 syscfg d9h pmu event register 6 default = 00h doze_timer pmi#27 smi: 00 = disable 01 = enable doze_0 (mva) 10 = enable doze_1 (mva) 11 = enable both 82C465MV/mva/mvb opti ? pa g e 138 912-3000-016 revision: 3.0 4.9.3 cpu thermal management unit thermal mana g ement hardware is implemented in the 82C465MV for monitorin g the level of cpu activit y and the operatin g temperature of the device. a flexible hardware scheme assesses cpu activit y to determine when it is neces- sar y to enter cool-down clockin g mode. in addition , an exter- nal sensor can force the 82C465MV permanentl y into cool- down clockin g mode accordin g to the parameters pro- g rammed for thermal mana g ement. in this wa y, a serious over-temperature condition cannot g et out of control ( as a result of thermal runawa y ) . 4.9.3.1 prediction of overtemp activity thermal mana g ement lo g ic is implemented in the 82C465MV for monitorin g the level of cpu activit y to determine its cur- rent draw , and thus approximate the operatin g temperature of the device. the most obvious wa y to do this would be to sim- pl y count the number of cpu clocks that occur in a g iven time period. however , a ripple counter runnin g in the 20-40mhz ran g e would consume a g reat deal of power. instead , 82C465MV lo g ic assesses cpu activit y periodicall y and keeps track of how often the cpu exceeds the safet y limits to determine whether automatic intervention is called for. operating temperature ranges the 82C465MV thermal mana g ement al g orithm identifies the temperature limits of an y cpu throu g h activit y level values that correspond with idle , e q uilibrium , and thermal runawa y conditions. ? idle condition - the cpu is cool to the touch. the 82C465MV is usin g apm stop clock or hardware doze mode to save power , and no real activit y is takin g place. this operational level constitutes the base level of activit y, so it does not re q uire a re g ister to hold the value. it is associated in the 82C465MV thermal mana g ement scheme with zero. ?e q uilibrium condition - the cpu is warm to the touch. it is operatin g at full speed for short bursts but fre q uentl y is at slow speed or stopped. the heat g enerated b y the cpu is dissipated at the same rate that it is produced. most active computer usa g e falls into this cate g or y, where apm or hardware doze mode operates fre q uentl y enou g h to allow safe operation. the 82C465MV thermal mana g ement scheme associates this temperature with e q uilibrium level bits , eql6:0. the value of these bits is referred to as eql throu g hout this section. ? thermal runawa y condition - the cpu is hot to the touch. it is runnin g at its full rated speed and g eneratin g heat faster than it can be dissipated , so its temperature increases. the pro g ram bein g used is active enou g h that apm or hardware doze mode cannot operate often enou g h to hold the temperature down. operatin g in this mode for an extended period ma y cause dama g e to the cpu. the 82C465MV thermal mana g ement scheme asso- ciates this temperature with overtemp limit bits , otl7:0. the value of these bits is referred to as otl throu g hout this section. accounting for cpu activity 82C465MV lo g ic fre q uentl y assesses cpu activit y, accordin g to the current cpu runnin g mode. each cpu run mode is associated with a power level increment as shown in table 4- 129. usin g these values , the 82C465MV can keep a runnin g count of the avera g e power bein g used b y the cpu in the internal 24-bit cpu activit y counter ( cnt ) . table 4-129 power levels assigned to each operating mode the 82C465MV must also be able to account for the cpu t y pe. for example , a clock-doubled or -tripled cpu at full speed will heat up much faster , y et at idle will cool down at approximatel y the same rate , as a non clock-multiplied cpu. the cpu efficienc y bits , cpue1:0 , are used to indicate the relative cpu current consumption and are explained below. the thermal mana g ement hardware keeps track of cpu activit y as follows. the lo g ic checks the current cpu operat- in g mode either 32k , 16k , 8k , or 4k times per second accord- in g to the cdho1:0 bits settin g as explained below. the thermal mana g ement lo g ic notes the current operatin g mode to account for the instantaneous cpu current consumption b y incrementin g or decrementin g the cpu activit y counter as follows. ? for all cpu operatin g modes , the lo g ic increments or dec- rements the counter b y the value listed in table 4-129 for the operatin g mode at that time. ?onl y for those modes with a power level increment above zero , the lo g ic also increments the cpu activit y counter b y the cpu efficienc y bits value. for example , if the cpu is sampled at full speed ( +2 ), and cpue1:0 = 2 , the activit y counter will be incremented b y 4. however , if the cpu is sampled at divide b y 8 ( C1 ), the counter will simpl y be decremented b y 1. the cpue value is not added in if the power level increment is zero or below because the cool-down rate is independent of cpu t y pe. current cpu operating mode power level increment full speed +2 divide b y 2 or 3 +1 divide b y 40 divide b y 8C1 divide b y 16 or more C2 apm stop clock C2 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 139 revision: 3.0 determination of operating temperature range periodicall y, the thermal mana g ement lo g ic compares the upper b y te of the cpu activit y counter to the overtemp limit ( otl ) and to the e q uilibrium level ( eql ) . this comparison takes place ever y 32 , 64 , 128 , or 256 seconds as pro- g rammed in the cool-down holdoff bits , cdho1:0. these bits also select the fre q uenc y of samplin g, at 32k , 16k , 8k , or 4k times per second respectivel y, such that the value accu- mulated in the cpu activit y count will , on avera g e , be the same whether a short or a lon g holdoff period is selected. the lo g ic acts on the comparison results as follows. ? if the upper b y te of the activit y count is g reater than or e q ual to otl , the thermal mana g ement unit initiates cool- down clockin g . ? if the upper b y te of the activit y count is above eql but below otl , eql is subtracted from the upper b y te of the cpu activit y counter and the result is returned to the counter. this scheme handles operation consistentl y above e q uilibrium level that ma y, over time , result in excessivel y hi g h cpu temperatures. ? if the upper b y te of the activit y count is e q ual to or below eql , the cpu activit y counter is simpl y cleared and the thermal mana g ement lo g ic starts a new detection period from zero ( idle condition ) . cool-down clocking cool-down clockin g takes place accordin g to the reduced clock rate pro g rammed into the cool-down clock rate bits , cdcr1:0. the 82C465MV keeps the cpu runnin g at the cool-down clockin g rate speed for the cool-down holdoff period multiplied b y the cool-down time-out value pro- g rammed. at the end of the period , the activit y counter is cleared and normal clockin g is restored. no activit y account- in g takes place while cool-down clockin g is en g a g ed. figure 4-8 thermal management block diagram cpu efficienc y ( cpue ) +3, +2, +1, 0 cpu operatin g mode +2, +1, 0, C1, C2 holdoff clock ( cdho ) sample @ 31, 61, 122, or 244 s limit check @ 32, 64, 128, or 256s overtemp limit ( otl ) e q uilibrium level ( eql ) en g a g e cool-down /2, /3, /4, /8 reset cpu activit y count ( cnt ) 24 bits 23 15 7 0 cnt 3 otl? yes no cnt 3 eql? yes no set newcnt = cool-down time-out ( cdto ) 1 to 20 minutes restore normal /1, /2, /3, /4, /8 clockin g ( cdcr ) clockin g oldcnt - eql 82C465MV/mva/mvb opti ? pa g e 140 912-3000-016 revision: 3.0 4.9.3.2 example a 25/75mhz cpu is bein g used with clock triplin g enabled. the cool-down clock rate is set to divide-b y -2 so that even when slowed down , the minimum clock speed will be above 12mhz. the cpu efficienc y bits are set to 3 because of the clock tripler. cool-down holdoff is set for 64 seconds; cool- down time-out is set for 3x; the e q uilibrium level is set to 40h; and the overtemp limit is set to 7fh. consider the situation after the cpu has run at full speed for one minute. the thermal mana g ement hardware is checkin g the cpu operatin g mode ever y 61 s ( 16 , 384 times per sec- ond ), and each time increments the cpu activit y counter b y 2 to account for the cpu runnin g at full speed and then b y 3 to account for the cpu efficienc y settin g . thus , the count is incremented b y 16 , 384 x 5 each second for 64 seconds , for a total count of 500000h. the value of the hi g h b y te is 50h; this value is compared to eql , which was set to 40h. since the activit y count exceeds the e q uilibrium level , eql is sub- tracted from the activit y count and the result ( 10h ) remains in the counter. however , the activit y count of 50h does not exceed the otl value of 7fh. therefore , no other action is taken. now consider the situation after the cpu has run at full speed for four minutes. after each 64-second interval , the hi g h-order activit y count b y te has been incremented b y 50h , and after the otl comparison is made the eql value of 40h has been subtracted off for a net increase of 10h. so after four minutes of operation , when the otl comparison is made , the activit y count of 80h is compared to the otl value of 7fh and an over-limit situation is detected. therefore , the thermal mana g ement hardware en g a g es cool- down clockin g at 25mhz/2 for three minutes ( 3 x 64 sec- onds ) . it then resets the cpu activit y counter , resumes nor- mal clockin g and monitorin g, and starts the whole detection process over a g ain. this situation would have been avoided if apm stop clock mode had been entered for at least ten seconds durin g each 64-second period. in that case , the thermal mana g ement hardware would have counted ( 16384 x 5 x 54 ) + ( 16384 x C2 x 10 ) = 3e8000h each time , j ust under the 40h e q uilibrium limit. the cpu activit y counter would have been reset each time and no thermal buildup would have been detected. 4.9.3.3 programming before pro g rammin g thermal mana g ement , the stpclk# mechanism must be set up for the cpu bein g used as described in section 4.9.1 , "stpclk# mechanism to change cpu speed" on pa g e 129. enablin g thermal mana g ement locks the stpclk# bits and prevents them from bein g altered until the next hardware reset. the thermal mana g ement option must be confi g ured b y set- tin g the bits in syscfg a5h , a6h , and a7h , and then settin g syscfg a5h bit 7 = 1. the re g ister settin g order is not important , but bit 7 of syscfg a5h must be set to 1 onl y after all other settin g s have been made. once bit 7 is set , none of the thermal mana g ement re g isters , nor the stpclk# bits ( syscfg 61h [ 2 ], 66h [ 0 ], and b0h [ 7:0 ]), can be written a g ain without resettin g the 82C465MV chip. table 4-130 shows the thermal mana g ement pro g rammin g re g isters and details re g ardin g the bits follow. table 4-130 thermal management registers 76543210 syscfg a5h thermal management register 1 default = 00h thermal mana g ement: 0 = disable 1 = enable e q uilibrium level ( eql6:0 ) : - this count corresponds to e q uilibrium operation. if the cpu activit y counter exceeds eql, eql is simpl y subtracted from the upper activit y count b y te and samplin g continues. if the count is below eql, the count is cleared. syscfg a6h thermal management register 2 default = 00h overtemp limit ( otl7:0 ) : - this count corresponds to an over-temperature situation. if the cpu activit y counter exceeds otl, the 82C465MV en g a g es cool-down clockin g . syscfg a7h thermal management register 3 default = 00h cpu efficienc y ( cpue1:0 ) : 00 = low power 01 = moderate 10 = hi g h 11 = ver y hi g h cool-down holdoff ( cdho1:0 ) : 00 = 32s 01 = 64s 10 = 128s 11 = 256s cool-down clock rate ( cdcr1:0 ) : 00 = /2 01 = /3 10 = /4 11 = /8 cool-down time-out ( cdto1:0 ) : 00 = 2x cdho 01 = 3x 10 = 4x 11 = 5x 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 141 revision: 3.0 thermal management enable bit syscfg a5h[7] - once written to 1 , none of the thermal mana g ement re g isters can be cleared without a s y stem reset. when read , this bit returns 1 onl y if cool-down clockin g is currentl y takin g place. cool-down holdoff bits syscfg a7h[5:4] - specif y the time period of observation to allow before checkin g whether to enable cool-down clockin g . cool-down clock rate bits syscfg a7h[3:2] - specif y the cpu clock divisor to use durin g cool-down clockin g . cool-down time-out bits syscfg a7h[1:0] - specif y the len g th of time , in terms of the cool-down holdoff selected , that the cool-down clockin g will continue before normal operation is restored. smi generation when the thermal mana g ement unit en g a g es or disen g a g es cool-down clockin g, an smi on pmi#25 can be g enerated. this feature is controlled throu g h syscfg dbh [ 6 ] . when this smi is bein g serviced , power mana g ement code can read syscfg a5h [ 7 ] to determine whether it was an entr y into or an exit from cool-down clockin g mode that caused the smi. pmi#25 is also shared with the epmi4 event. if the smi from epmi4 is also enabled , on entr y to the smi software must check the state of the epmi4 si g nal to determine whether the reason for the smi is the external epmi4 event or cool-down clockin g entr y /exit. 4.9.4 emergency overtemp sense it is possible for an external sensor to force the 82C465MV into cool-down clockin g mode accordin g to the parameters pro g rammed for thermal mana g ement. when low , the epmi2 input can cause the 82C465MV to enter cool-down clockin g mode. the existin g smi enable bits for epmi2 are still opera- tional re g ardless of the settin g of the emer g enc y overtemp enable bit. therefore , an overtemp condition can also be pro- g rammed to cause an smi so that the power mana g ement firmware will be made aware of the situation and instruct the user to shut down the s y stem. in this wa y, a serious over- temperature condition cannot g et out of control. the chip will remain in cool-down clockin g mode , usin g the rate specified in syscfg a7h , cpu thermal mana g ement re g ister 3 , ( defaults to divide-b y -2 ) as lon g as the epmi2 input remains tri gg ered. the tri gg er specifications are the same as those for tri gg erin g the smi: syscfg 40h [ 2 ] selects whether a hi g h level or a low level is active , and this same bit selects whether a hi g h level or a low level will en g a g e cool- down clockin g . the thermal mana g ement unit does not need to be enabled to use this feature. epmi2 can be used as the overtemp sense input even when the epmi2 function has been moved to an external 74153 multiplexer ( when the standard dackmux interface feature has been selected ) . 4.9.4.1 programming the emer g enc y overtemp sense option is enabled b y writin g syscfg dbh [ 6 ] as explained previousl y ( smi generation section , this pa g e ) . once written , this bit cannot be chan g ed without a hard reset of the chip. when syscfg dbh [ 6 ] = 1 , entr y into or exit from cool-down clockin g mode causes pmi#25 and an smi. if the epmi2 event is also pro g rammed to cause an smi , the followin g situ- ation can occur. 1. the thermal sensor input chan g es state , causin g pmi#2 and an smi. 2. power mana g ement code services the smi. 3. the thermal mana g ement unit g enerates a stop clock re q uest. 4. once the cpu g enerates a stop g rant c y cle , the chipset reduces the clock speed to enter cool-down clockin g mode. 5. at this point , pmi#25 is g enerated alon g with another smi. therefore , two smis will have been g enerated. on exit from cool-down clockin g mode , onl y one smi will be g enerated , since the active-to-inactive transition on epmi2 does not cause another smi. power mana g ement software must be able to anticipate this situation and deal with it appropriatel y . 82C465MV/mva/mvb opti ? pa g e 142 912-3000-016 revision: 3.0 4.10 suspend and resume the 82C465MV offers the abilit y to halt operations at extremel y low power y et retain all its pro g rammin g, called suspend. the chipset will respond to interrupts to determine that a return to normal operation , called resume , is neces- sar y . 4.10.1 suspend mode suspend mode provides a si g nificant level of power conser- vation. the suspend initiation event , either a ke y or button depression or a time-out smi , calls a software routine in smm code to save the current state of the s y stem for complete res- toration at some later time. in this mode , most s y stem power can be shut down while still retainin g the abilit y to restore the previous context. the 82C465MV can either stop the clock to a still-powered cpu , or en g a g e leaka g e controls with a cpu that must be powered down durin g suspend. the leaka g e control function is enabled b y either floatin g or drivin g low all critical interface nodes to reduce power consumption to a bare minimum. the 82C465MV enters suspend mode when syscfg 50h [ 0 ] is set to 1. software must control this event , even thou g h a timer time-out ma y have initiated the process , because cpu processin g must be completed in an orderl y fashion. upon resumin g from suspend mode , the controllin g code must clear the suspend pmi event , pmi#7 , b y writin g syscfg 5ch [ 7 ] = 1. otherwise , the chip will never leave suspend mode the next time syscfg 50h [ 0 ] is set to 1. the re g isters shown in table 4-131 select the state of various si g nals durin g suspend mode. refer to the resume event section that follows to determine how to select the events that will cause the chip to resume operation after suspend. reload timers on resume (syscfg 59h[6]) - the s y stem timers can be restarted to prevent false time-outs upon resumin g from suspend mode. table 4-131 suspend control register bits 76543210 syscfg adh feature control register 3 default = 00h cpu power state in suspend: 0 = powered 1 = 0 volt syscfg 50h pmu control register 5 default = 00h start suspend ( wo ) : 1 = enter suspend mode syscfg 59h pmu event register 2 default = 00h reload timers on resume? 0 = no 1 = yes 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 143 revision: 3.0 4.10.1.1 suspend mode power savings the 82C465MV can be preset in various wa y s before enter- in g suspend mode in order to minimize the current consump- tion while suspended. resistor control registers the resistor control re g isters control and/or disable the auto- matic internal pull-down resistors on various lines durin g sus- pend mode. these re g isters are described in the chip-level power conservation features section of this document. short-pulse refresh the short pulse refresh mechanism should be en g a g ed for lowest dram power consumption durin g suspend. the sus- pend refresh rate is selected throu g h syscfg 67h [ 6:5 ], the same bits that select the refresh rate for active operation. however , there is a ma j or difference between active mode refresh and suspend mode refresh: active mode refresh pulse width is controlled b y the oscclk input clock , while the suspend mode refresh pulse width is g enerated from the sqwin clock and therefore has the same pulse width as that clock. for a 32khz input , this pulse width is 15 s which will cause dram to consume extra power. settin g syscfg a1h [ 6 ] = 1 allows the refresh pulse width to be narrowed to approximatel y 100ns and should alwa y s be selected if appropriate for the dram in use. self-refresh dram suspend refresh can be eliminated alto g ether throu g h syscfg 66h [ 7 ] for self-refresh dram. if none is selected for suspend refresh , onl y a sin g le low pulse se q uence is g en- erated to put the dram into self-refresh mode. interrupt scan rate the lo g ic can scan for interrupts at a slower rate , at 122 s intervals instead of 280ns intervals. this feature uses the sqwin clock instead of the 14.318mhz clock to g enerate kbclk and kbclk2 , so an y ke y board controller in use must be able to tolerate this slower clockin g speed. syscfg 66h [ 6 ] controls the kbclk rate to be applied durin g suspend mode. note that a ma j or reduction of power consumption can come from switchin g off the 14.318mhz clock g enerator circuit of the clock g enerator chip in use when kbclk runs from sqwin. suspend mode hold control assertin g hold to the cpu before stoppin g the clock is used to tristate the cpu si g nals durin g suspend. this feature ma y or ma y not be useful , as determined b y the s y stem desi g n. ?settin g suspend mode hold control bit , syscfg 66h [ 4 ], = 0 drives hold hi g h durin g suspend. this settin g is use- ful if some devices on the vl bus are powered off durin g suspend. man y cpus drive output si g nals to their last state while in stop g rant state , which could power up unpowered devices on the bus. these cpus tristate the outputs if in stop g rant state and g ive the s y stem hlda. ?settin g suspend mode hold control bit , syscfg 66h [ 4 ], = 1 does not drive hold durin g suspend. this settin g is useful in con j unction with the zero-volt cpu suspend option described in the special cpu interface support section , because it allows all cpu interface si g nals to g o low at suspend time. the correct settin g of the bit depends on the vl-bus power- down scheme used in the desi g n. table 4-132 suspend mode power saving feature bits 76543210 syscfg 66h pmu control register 8 default = 00h suspend refresh: 0 = slow 1 = none ( for self-refresh dram ) suspend kbclk source: 0 = 14mhz/2 1 = 32khz/2 assert hold durin g suspend? 0 = yes 1 = no syscfg a1h feature control register 2 default = 00h suspend refresh pulse g eneration: 0 = wide 1 = ~100ns 82C465MV/mva/mvb opti ? pa g e 144 912-3000-016 revision: 3.0 suspend refresh pulse width control the suspend mode refresh pulse on the 82c465 series part is g enerated b y g ate dela y s. these g ate dela y s var y si g nifi- cantl y accordin g to the volta g e at which the part operates. at 5.0v core operation , the pulse width mi g ht be 150-250ns. if the core operates at 3.3v , the pulse width mi g ht be 400- 500ns. therefore , the 82C465MVb part provides syscfg 3fh [ 6 ] to select fewer g ates in the dela y path. at its default settin g of 0 , the pulse width is comparable with that of the 82C465MVa part. when set to 1 , the pulse width is approxi- matel y one half of the normal value. the settin g of 1 is proba- bl y the best settin g for 3.3v core operation. table 4-133 suspend refresh pulse width control syscfg 67h pmu control register 9 default = 00h refresh rate active or suspend mode: 00 = 15 s ( 30 s in suspend if syscfg a1h [ 6 ] = 0 ) 01 = 30 s 10 = 61 s 11 = 122 s table 4-132 suspend mode power saving feature bits (cont.) 76543210 76543210 syscfg 3fh misc. control register default = 00h suspend refresh pulse width: 0 = normal 1 = reduced (mvb) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 145 revision: 3.0 4.10.2 resume event a certain set of interrupt events can be enabled to resume the s y stem from suspend mode. the desired interrupts are g rouped into a sin g le event , called rsmgrp. rsmgrp can be enabled to g enerate an smi if desired. the ri input and the susp/rsm input can also tri gg er a resume , and can also be enabled to g enerate an smi if desired. an y one or more of the rsmgrp , ri , and susp/rsm events are called a resume event. 4.10.2.1 epmi/irq events the re g isters at syscfg 6ah and b1h select the epmi and irq source ( s ) that will be allowed to tri gg er the s y stem out of suspend mode. once selected , settin g syscfg 5fh [ 5 ] = 1 enables the rsmgrp g loball y . on resume , an smi can be g enerated either from the epmi events ( throu g h syscfg 58h and d9h ) or the pmi#6 event ( throu g h syscfg 59h ) . however , since the s y stem usuall y is still in smm when the resume takes place , smi g eneration is not normall y neces- sar y . the irq and epmi resume enablin g bits are shown in table 4-134. default for all bits is disabled. a risin g ed g e on the enabled si g nal causes the resume event for all selections except irq8; it is a fallin g ed g e on irq8 that resumes oper- ation. 4.10.2.2 susp/rsm and ri events when the ri input pin to gg les enou g h to exceed the count set in syscfg 5fh [ 3:0 ], and syscfg 5fh [ 4 ] = 1 , pmi#6 is g enerated to exit suspend mode. si g nal ri should be hi g h for a minimum of 240ms and low for a minimum of 60ms when chan g in g states. the ri input is sampled with a 32khz clock; therefore rapid or unstable transitions ma y lead to unreliable countin g . the susp/rsm input pin is alwa y s enabled to resume the s y stem , and should be pulled hi g h if it will not be used in the s y stem desi g n. resumin g from susp/rsm g enerates pmi#6. table 4-134 resume event registers 76543210 syscfg 6ah rsmgrp irq register 1 default = 00h epmi2 resume: 0 = disable 1 = enable epmi1 resume: 0 = disable 1 = enable irq8 resume: 0 = disable 1 = enable irq7 resume: 0 = disable 1 = enable irq5 resume: 0 = disable 1 = enable irq4 resume: 0 = disable 1 = enable irq3 resume: 0 = disable 1 = enable irq1 resume: 0 = disable 1 = enable syscfg b1h rsmgrp irq register 2 default = 00h epmi4 resume: 0 = disable 1 = enable epmi3 resume: 0 = disable 1 = enable irq15 resume: 0 = disable 1 = enable irq14 resume: 0 = disable 1 = enable irq12 resume: 0 = disable 1 = enable irq11 resume: 0 = disable 1 = enable irq10 resume: 0 = disable 1 = enable irq9 resume: 0 = disable 1 = enable syscfg 5fh pmu control register 7 default = 00h rsmgrp irqs can resume s y stem? 0 = no 1 = yes transitions on ri can resume s y stem? 0 = no 1 = yes number of ri transitions to cause resume 82C465MV/mva/mvb opti ? pa g e 146 912-3000-016 revision: 3.0 once a resume event has occurred , syscfg 6bh [ 2:0 ] should be read to determine the source ( s ) . if 6bh [ 1 ] = 1 , a read of syscfg 6ah and b1h will return the latched state of the an y of the epmi or irq lines that were ori g inall y enabled for resume tri gg erin g . the latched resume irq and epmi source information in 6ah and b1h is available until the pmi#6 bit ( syscfg 5ch [ 6 ]) is eventuall y written to 1 to clear the pmi g enerated. syscfg 50h [ 1 ] = 1 as lon g as the resume pmi#6 remains active. table 4-135 resume sources (read-only) 76543210 syscfg 50h pmu control register 5 default = 00h read y to resume ( ro ) : 0 = not in resume 1 = read y to resume pmu mode ( ro ) : 0 = nothin g pendin g 1 = suspend active ( clear pmi#6 ) syscfg 6bh resume source register default = 00h cisa sel#/ atb# low caused resume ( ro ) ? 0 = no 1 = yes (mvb) susp/rsm caused resume ( ro ) ? 0 = no 1 = yes rsmgrp caused resume ( ro ) ? 0 = no 1 = yes ri caused resume ( ro ) ? 0 = no 1 = yes 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 147 revision: 3.0 4.10.3 chip-level power conservation features a central desi g n g oal of the 82C465MV was to incorporate power-reducin g features wherever possible. to this end , sev- eral innovative methods of power conservation are imple- mented. 4.10.3.1 automatic keeper resistors since there are times durin g normal operation in which the cpu tristates man y of its output si g nals and no other source is drivin g these si g nals , the lines tend to float between lo g ic transition levels. when this results in an oscillation , a sub- stantial amount of current is consumed. for this reason , external pull-up or pull-down resistors are t y picall y connected on these lines. even if resistors are inte g rated into the chipset itself , considerable current would be consumed durin g nor- mal operation when the lo g ic is active and is drivin g a g ainst these resistors. the 82C465MV circuitr y provides the option of internal 50k w pull-down resistors on certain lines. the resistors are auto- maticall y en g a g ed onl y durin g bus hold and suspend mode. also , the chip provides an option to enable the resistors all the time. it is theoreticall y possible that durin g lon g periods with iochrdy low , the temporar y tristate condition of the cpu and 82C465MV interfaces could consume more power than would be needed on avera g e to leave the pull-down resistors en g a g ed constantl y . the s y stem desi g ner must determine the settin g that is appropriate. the resistors are on ca31 , ca [ 25:2 ], cd [ 31:0 ], be3:0# , w/r# , d/c# , and m/io#. the resistors serve to prevent the buses from floatin g and consumin g power durin g suspend mode , as well as to hold the upper address lines low and the cpu control lines inactive durin g bus hold c y cles to prevent the lo g ic from misinterpretin g c y cle t y pes and destinations durin g dma operations. this feature can be used safel y with the zero-volt cpu suspend option , since the resistors alwa y s pull down when en g a g ed. settin g syscfg a0h [ 6 ] = 1 enables this feature. the 82C465MV additionall y mana g es the ferr# pin when this feature is enabled , providin g a pull-up resistor that is en g a g ed while the chip is active and a pull-down resistor when the chip is in suspend mode. this feature eliminates the need for external control of ferr# dependin g on the t y pe of cpu installed. the re g isters also control the dackmux0- 2 si g nal states durin g suspend , re g ardless of where these si g nals have been relocated on the chip. table 4-136 resistor control registers note: notice that ferr# has an internal pull -up resistor. 76543210 syscfg a0h feature control register 1 default = 00h automatic internal resistors: 0 = disable 1 = enable syscfg d4h resistor control register 1 default = 00h ca31, ca [ 25:2 ] , be [ 3:0 ] # pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved cd [ 31:0 ] pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved m/io#, d/c#, w/r# pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved syscfg d5h resistor control register 2 default = 00h dackmux control durin g suspend: 00 = pull resistor-e q uipped lines low, drive others low 01 = tristate all lines ( 463mv mode ) 10 = drive 100b on dackmux2-0 11 = reserved ferr# pull-up resistor control: 0 = alwa y s enabled 1 = alwa y s disabled 82C465MV/mva/mvb opti ? pa g e 148 912-3000-016 revision: 3.0 4.10.3.2 zero-volt cpu suspend most cpus desi g ned for portable applications consume ne g - li g ible power when their input clock is stopped. some cpus draw too much power to be left powered when the s y stem is in suspend mode , y et it is still desirable to obtain the rapid start-up available onl y throu g h cop y in g cpu context into dram and keepin g dram alive. therefore , the 82C465MV cpu interface provides a zero-volt suspend option. settin g syscfg adh [ 5 ] = 1 enables zero-volt cpu sus- pend. when set , the 82C465MV will condition its outputs dur- in g suspend assumin g that the cpu has been powered down completel y . the affected 82C465MV output si g nals are listed in section 3.6 , "pin signal characteristics" on pa g e 16. si g - nals that would normall y be maintained hi g h to the cpu while in suspend mode are instead tristated. this feature is g enerall y used in con j unction with a feature on the sreset pin which , in this case , is used as the g eneral- purpose cpu reset ( not as a software reset ) . b y settin g syscfg adh [ 3 ] = 1 , the sreset si g nal will to gg le on resume from suspend to reset a cpu that has been pow- ered-down. refer to the special cpu interface support sec- tion of this document for more information. note also that when syscfg adh [ 5 ] = 1 , cpurst will alwa y s be g enerated upon resumin g . table 4-137 zero-volt cpu suspend register bits 76543210 syscfg adh feature control register 3 default = 00h cpu power state in suspend: 0 = powered 1 = 0 volt sreset operation: 0 = normal 1 = to gg le on resume 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 149 revision: 3.0 4.10.3.3 clock stretching the re g ister bits in table 4-138 are used to enable power- savin g features for various s y stem clocks. the cpu clock stretch functions should be enabled onl y for a totall y static cpu , and then onl y when the cpu clock is set to /1 or /4. the atclk stretch function can be enabled for both 1x and 2x cpus. 4.10.3.4 stopping ipc clock when not in use settin g syscfg 50h [ 4 ] = 0 stops the clock g oin g to the inter- nal 82c206 ipc module. primaril y this settin g affects the 8254-t y pe clock/timer/counter circuit. if the timer will not be used to maintain the dos s y stem clock , substantial power savin g s can be achieved b y disablin g this clock , and turnin g off the osc14 clock g enerator if possible. althou g h kbclk and kbclk2 are derived from the 14mhz clock directl y, the y are not affected b y this bit settin g . table 4-139 hi g hli g hts this re g ister bit. 4.10.3.5 stopping kbclk and kbclk2 the 82C465MVa part allows the kbclk and kbclk2 out- puts to be driven low. this feature is useful durin g suspend mode to stop the ke y board and irq/drq scannin g clocks when those devices are powered down. table 4-140 shows the re g ister bit used for pro g rammin g this feature. table 4-138 clock stretch register table 4-139 pmu control register - syscfg 50h table 4-140 kbclk/kbclk2 stop control 76543210 syscfg 5eh clock stretch register default = 00h stretch mem- or y code c y cle: 0 = disable 1 = enable stretch write c y cle: 0 = disable 1 = enable stretch read c y cle: 0 = disable 1 = enable stretch i/o c y cle: 0 = disable 1 = enable stretch mem- or y data c y cle: 0 = disable 1 = enable atclk when not in c y cle: 0 = runs 1 = stopped at clock stretch: 0 = as y nc 1 = s y nc 76543210 syscfg 50h pmu control register 5 default = 00h 14.3mhz to ipc: 0 = enable 1 = disable 76543210 syscfg 79h pmu control register 11 default = 00h kbclk/ kbclk2 control: 0 = normal operation 1 = stopped in low state (mva) 82C465MV/mva/mvb opti ? pa g e 150 912-3000-016 revision: 3.0 4.11 power control latch and pio pins there are 12 peripheral power pins ( ppwr0-11 ) that are used to control power to individual peripherals throu g h exter- nal 74373 latches. each latch pin is controlled with its individ- ual control bits in the confi g uration re g isters at syscfg 54h , 55h , and abh. four g eneral purpose i/o pins are also provided for control- lin g or monitorin g external devices without the need for addi- tional ttl. these pins also offer certain prepro g rammed functions that are commonl y useful in s y stem desi g ns. 4.11.1 power control latch the value latched b y ppwrl from the ma bus extends from ppwr0 throu g h ppwr11 , providin g four useful power con- trol si g nals for up to a dozen devices if all 12 bits are latched. ma11 is an optional si g nal , so ppwr11 is available onl y if ma11 is enabled as explained in section 4.4.1 , "dram con- troller hardware options" on pa g e 48. 4.11.1.1 hardware considerations the power control scheme uses the ma [ 11:0 ] si g nals that normall y address dram to additionall y provide the inputs to a 74373-t y pe latch. if all 12 si g nals will be used , two '373 devices ( or a different combination , such as one '373 and one half of an '11873 ) are needed. the ppwrl si g nal from the 82C465MV is an active hi g h si g nal and latches the ma [ 11:0 ] si g nals on the latch output on its fallin g ed g e. the pins ppwr0 and ppwr1 have a recover y dela y time associated with them when doin g the suspend/resume func- tion. these two pins can be used as a dela y control for some component that needs some time to become stable once power is restored. for example , after turnin g off the power to the clock oscillator durin g suspend mode , the resume func- tion will restore power to the clock oscillator and wait until the clock has had time to stabilize before continuin g the resume process. ppwr10 provides the rsmrst# function. on hardware reset and on resumin g from suspend mode , ppwr10 simpl y pulses low to g enerate a reset for an y peripherals that were powered down durin g suspend. while also available directl y from pin 185 as a strap-selected option , rsmrst# is alwa y s provided on ppwr10 re g ardless of the strappin g option so that when pin 185 is reassi g ned from epmi2 to dackmux1 ( the alternative dackmux interface option ), rsmrst# will still be available. refer to the reset lo g ic section for rsmrst# timin g information. durin g reset , the ppwrx latch si g nal ( ppwrl ) is pulsed to set the ppwrx si g nals to a known state. after reset ppwr0- 3 and ppwr8-11 are set to '0'; ppwr4-7 are set to '1'. the ppwrx si g nals will remain in this state until the y are updated b y writin g to syscfg 54h , 55h , and abh. note: the ma [ 11:0 ] pins and ppwrl are on the cpu power plane. in a mixed-volta g e s y stem , 3.3v-inputs to a 5.0v-powered latch will result in excessive cur- rent drain for an y input that remains hi g h durin g idle periods ( around 1ma per input in suspend mode ) . the desi g ner should make provisions to minimize the effect of this condition. 4.11.1.2 signal considerations there is the possibilit y of a spike on the 82C465MVa or mvb ppwrl si g nal. the amplitude is g reat enou g h to latch an incorrect value on the ppwr latch. the spike is noticeable when doin g flopp y or ide accesses. it is up to 4ns wide and can reach 1v in amplitude. ground bounce internal to the chip on the other nearb y si g - nals is causin g the spike , a result of ppwrl bein g the last si g nal in the 3.3v cpu power plane. ad j acent si g nals are in the isa power plane , and the nearest g round pin to ppwrl is 12 pins awa y . the workaround is to dampen the spike b y usin g series termi- nation on the ppwrl line as shown in the fi g ure below. the r-c values depend on the board la y out; a g ood startin g point is r=~75ohm and c=~1000pf. ppwrl is not a time-critical si g nal. figure 4-9 damping r-c for ppwrl spike 4.11.1.3 programming syscfg 54h , 55h , and abh set the power control latch out- puts. the upper bits [ 7:4 ] of each re g ister select whether the correspondin g bits [ 3:0 ] should be used to chan g e the latch; if the enable bit is 0 , the current latch settin g will not be chan g ed when the re g ister is written. resume recovery time syscfg 68h [ 3:2 ] determine the recover y time from ppwr1- 0 active after a resume until the end of reset. the rsmrst# ppwrl 82c465 en 373 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 151 revision: 3.0 si g nal and/or rst4# is active durin g this recover y time. the clock is g uaranteed to be active for at least the last 1/8 of the recover y time. these bits are not affected b y syscfg 68h [ 1:0 ] . these bits can be overridden b y settin g syscfg beh [ 0 ] = 1 , in which case the resume recover y time will alwa y s be 1 sec- ond. ppwr1-0 suspend auto toggle feature s7scfg 68h [ 0 ] and 68h [ 1 ] enable ppwr0 and 1 , respec- tivel y, to automaticall y to gg le when enterin g and exitin g sus- pend mode. usin g ppwr0 as an example: when bit 0 = '1' and the chipset has g one into suspend mode , ppwr0 g ets set to the inverse of syscfg 54h [ 0 ] ; mask bit syscfg 54h [ 4 ] is i g nored. when exitin g suspend mode , ppwr0 is set to the bit 54h [ 0 ] settin g, followed b y the recover y time dela y set in syscfg 68h [ 3:2 ] before continuin g the resume operation. table 4-130 shows the above discussed re g isters. table 4-141 ppwrl programming registers 76543210 syscfg 54h power control latch register 1 default = x0h enable [ 3:0 ] to write latch lines ppwr3-0: 0 = disable 1 = enable read/write data bits for ppwr3-0 - default 0000: 0 = latch output low 1 = latch output hi g h syscfg 55h power control latch register 2 default = xfh enable [ 3:0 ] to write latch lines ppwr7-4: 0 = disable 1 = enable read/write data bits for ppwr7-4 - default 1111: 0 = latch output low 1 = latch output hi g h syscfg abh pmu control register 3 default = x0h enable [ 3:0 ] to write latch lines ppwr11-8: 0 = disable 1 = enable read/write data bits for ppwr11-8 - default 0000: 0 = latch output low 1 = latch output hi g h syscfg 68h clock source register 3 default = 00h resume recover y time: 00 = 8ms 10 = 128ms 01 = 32ms 11 = 30 s i g nored if syscfg beh [ 0 ] = 1 ppwr1-0 auto to gg le: 0 = disable 1 = enable syscfg beh idle reload event enable register 2 default = 00h override syscfg 68h [ 3:2 ] : 0 = no 1 = recover time 1s 82C465MV/mva/mvb opti ? pa g e 152 912-3000-016 revision: 3.0 4.11.2 programmable i/o pins the pro g rammable i/o ( pio ) pins provide g eneral purpose i/o pins for controllin g and/or monitorin g s y stem operations. several of these pins have specialized options that are linked into the 82C465MV lo g ic. ? pio3 can be redefined as the stpgnt# output for those cpus that provide a specific acknowled g e si g nal , not j ust a special stop g rant c y cle , to the chipset. certain c y rix and ti cpus , and the ibm blue li g htnin g cpu , provide this si g nal. ? pio2 can be defined as an output to indicate when the cpu is in its full-speed mode , or as an input for an external isa bus clockin g source ( atclkin ) . ? pio1 can be redefined as the zero wait state input nows# from the isa bus. when enabled and active , this si g nal can reduce the time re q uired to complete an isa bus c y cle to improve s y stem speed. ? pio0 can be redefined as the lreq# input from the vl bus so that vl bus masters can re q uest ownership of the bus. when pio0 is redefined in this wa y, the dack2# pin also g ets redefined as the lgnt# output to the vl bus. when the y are not assi g ned special functions , the pio pins are set for input or output and their data read or written throu g h the re g isters at syscfg 56h and 57h. note: if a pio pin will not be used , it should either be pro- g rammed as an output pin or should be pulled up externall y if left as an input. otherwise , durin g sus- pend mode the pin will float and cause hi g h power consumption. 4.11.2.1 pio3/stpgnt# pin select when pin 171 is stpgnt# , also set syscfg 57h [ 3 ] to input mode. stpgnt# is for cpus that use a dedicated stop g rant si g nal pin to acknowled g e a stop re q uest. 4.11.2.2 pio2/cpuspd pin select when pin 172 is cpuspd , also set syscfg 57h [ 2 ] to output mode. cpuspd indicates whether the cpu is at full speed or is slowed down. note that output settin g s on pio2 ma y con- flict with atclkin feature set b y syscfg a0h [ 4 ] . 4.11.2.3 pio1/nows# pin select when pin 173 is nows# , also set syscfg 57h [ 1 ] to input mode. nows# is the isa bus si g nal that re q uests a shorter c y cle if possible. table 4-142 pio pin registers 76543210 syscfg 56h pio pin control register default = x0h write mask of syscfg 56h [ 3:0 ] : 0 = disable writes on correspondin g bit [ 3:0 ] 1 = enable bit [ 3:0 ] writes to pio pins read/write data for pio3-0: read: returns value present at pin. write: sets pin value if direction bit is set to 1. syscfg 57h pmu control register 6 default = 00h pio3 direction: 0 = input 1 = output pio2 direction: 0 = input 1 = output pio1 direction: 0 = input 1 = output pio0 direction: 0 = input 1 = output syscfg 66h pmu control register 8 default = 00h pin 171 function: 0 = pio3 1 = stpgnt# pin 172 function: 0 = pio2 1 = cpuspd pin 173 function: 0 = pio1 1 = nows# syscfg a0h feature control register 1 default = 00h enable local bus master support: 0 = pio0 and dack2# 1 = lreq# and lgnt# pin 172 function: 0 = pio2 ( or cpuspd ) 1 = atclkin 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 153 revision: 3.0 4.11.3 programmable chip select feature the 82C465MV provides pro g rammable chip select features that re q uire no chip si g nals to be sacrificed. a total of four pro g rammable chip selects are available , and can decode either memor y c y cles or i/o c y cles. for i/o chip select decod- in g, g ranularit y can be specified to-the-b y te , decodin g a total of 10 bits. syscfg a7h [ 7 ] determines whether the a [ 15:10 ] bits must be 0 or will be i g nored. for rom chip select decod- in g, g ranularit y is to 16kb blocks an y where in the isa address space ( 16mb ) . note that the memor y chip select feature should be used cau- tiousl y for roms residin g below 1mb. since the rom to be selected is on the sd bus , the xd bus buffer ( if used ) ma y be directed toward the 82C465MV chip for memor y reads and could conflict with sd bus roms. therefore , alwa y s set the romcs# g eneration re g isters ( described in section 4.4.6 , "system rom and shadow ram" on pa g e 54 ) to prevent xd bus romcs# conflicts with sd bus roms. in hardware desi g n , the chip select si g nals are decoded as follows. usin g 7432 g ates , first q ualif y atcyc# with aen to obtain a si g nal called csg# here. then: ? csg0# = csg# ored with ma8 ? csg1# = csg# ored with ma9 ? csg2# = csg# ored with ma6 ? csg3# = csg# ored with ma7. the re q uired re g isters are shown in table 4-143 throu g h table 4-146. table 4-143 programmable chip select 0 registers 76543210 syscfg 4ah chip select 0 base address register default = 00h csg0# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 4bh chip select 0 control register default = 00h csg0# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg0# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : a '1' in a particular bit means that the correspondin g syscfg 4ah [ 3:0 ] is not compared. this is used to determine address block size. syscfg bfh chip select granularity register default = 0fh csg0# base address: a0 ( i/o ) a14 ( memor y) csg0# mask bit: a0 ( i/o ) a14 ( memor y) syscfg b3h chip select cycle type register default = 00h csg0# rom width: 0 = 8-bit 1 = 16-bit csg0# c y cle t y pe: 0 = i/o 1 = romcs 82C465MV/mva/mvb opti ? pa g e 154 912-3000-016 revision: 3.0 table 4-144 programmable chip select 1 registers 76543210 syscfg 4ch chip select 1 base address register default = 00h csg1# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 4dh chip select 1 control register default = 00h csg1# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg1# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : a '1' in a particular bit means that the correspondin g bit 4ch [ 3:0 ] is not compared. this is used to determine address block size. syscfg bfh chip select granularity register default = 0fh csg1# base address: a0 ( i/o ) a14 ( memor y) csg1# mask bit: a0 ( i/o ) a14 ( memor y) syscfg b3h chip select cycle type register default = 00h csg1# rom width: 0 = 8-bit 1 = 16-bit csg1# c y cle t y pe: 0 = i/o 1 = romcs table 4-145 programmable chip select 2 registers 76543210 syscfg bah chip select 2 base address register default = 00h csg2# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg bbh chip select 2 control register default = 00h csg2# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg2# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg bah [ 3:0 ] is not compared. this is used to determine address block size. syscfg bfh chip select granularity register default = 0fh csg2# base address: a0 ( i/o ) a14 ( memor y) csg2# mask bit: a0 ( i/o ) a14 ( memor y) syscfg b3h chip select cycle type register default = 00h csg2# rom width: 0 = 8-bit 1 = 16-bit csg2# c y cle t y pe: 0 = i/o 1 = romcs 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 155 revision: 3.0 4.11.3.1 programmable chip select limitations the pro g rammable chip select feature uses the ma6-ma9 si g nals and the atcyc# pin to g enerate a chip select si g nal. this si g nal can be further q ualified as i/o read , i/o write , memor y read , or memor y write onl y . however , there are sev- eral desi g n issues surroundin g this feature. qualification with aen the shared nature of the si g nals involved dictates that chip selects cannot g o active durin g an y c y cle where the ma lines are used otherwise ( i.e. for dram accesses ) . therefore , the chip-selected device cannot be accessed durin g a dma c y cle. the data book and reference schematics specif y that aen be used to block the chip select durin g dma and refresh. but when the atclk used is not s y nchronous to the cpu clock , atcyc# will g o active when a dma c y cle takes place before res y nchronization allows the aen line to g o active. there- fore , opti now recommends usin g the hlda si g nal from the cpu instead of usin g aen to block chip selects durin g dma and refresh. s y stem desi g ners usin g this approach must be aware that hlda is usuall y a 3.3v si g nal , while aen is a 5v si g nal. in desi g ns where the pro g rammable chip select line is used solel y as a raw decode , and the connected device also uses isa command lines to q ualif y the operation , aen is still an acceptable solution. glitch caused by gate delays whenever atcyc# is g enerated for use as a pro g rammable chip select , the ma6-9 pins must be internall y switched from their memor y controller function to their chip select function. the multiplexer lo g ic used internal to the chip bases its switchin g on the same atcyc# si g nal as is driven externall y . therefore , atcyc# arrives external to the chip several nano- seconds before the new ma6-9 values take effect. a g litch can occur durin g this time. if this situation is unacceptable , an extra dela y can be intro- duced externall y in atcyc#. one wa y to do this would be to insert an extra g ate in the path for atcyc#. another wa y would be to use a slower lo g ic famil y for the 7432 that q uali- fies atcyc# with aen , and use faster lo g ic for the 7432 g ates that g ate the q ualified atcyc# si g nal with the ma lines. table 4-146 programmable chip select 3 registers 76543210 syscfg bch chip select 3 base address register default = 00h csg3# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg bdh chip select 3 control register default = 00h csg3# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg3# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg bch [ 3:0 ] is not compared. this is used to determine address block size. syscfg bfh chip select granularity register default = 0fh csg3# base address: a0 ( i/o ) a14 ( memor y) csg3# mask bit: a0 ( i/o ) a14 ( memor y) syscfg b3h chip select cycle type register default = 00h csg3# rom width: 0 = 8-bit 1 = 16-bit csg3# c y cle t y pe: 0 = i/o 1 = romcs 82C465MV/mva/mvb opti ? pa g e 156 912-3000-016 revision: 3.0 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 157 revision: 3.0 5.0 register summary an indexin g scheme is used to access the s y stem control re g ister space ( syscfg ) . port 022h is used as the index re g ister and port 024h as the data re g ister. each access to a re g ister within this space consists of: 1 ) a write to port 022h , specif y in g the desired re g ister in the data b y te , 2. followed b y a read or write to port 024h with the actual re g ister data. the index resets after ever y access; so ever y data access ( via port 024h ) must be preceded b y a write to port 022h even if the same re g ister is bein g accessed consecutivel y . note that not all re g ister bits are both readable and writable. moreover , some re g ister bits that can be written return differ- ent information when read. therefore , it is g ood pro g rammin g practice to maintain an up-to-date cop y of all re g ister settin g s in s y stem ram. re g ister definitions that are specific to the 82C465MVa or 82C465MVb versions of the product are indicated for each bit with an mva or and mvb , respectivel y, in parentheses. if a bit is desi g nated as such , it is reserved for previous ver- sions of the product. definitions marked as mva are also available in the mvb version. re g isters without the mva or mvb markin g appl y to all three versions. note: all reserved re g isters must be written to 0 unless oth- erwise specified. all re g isters are read/write unless otherwise speci- fied. table 5-1 syscfg register space 76543210 syscfg 30h control register 1 default = 40h 82c46x product indicator ( ro ) : 00 = 82c463/463mv 01 = 82C465MV 10 = 82C465MVa 11 = 82C465MVb pin 186 function: 0 = master# 1 = ri turbo vga ( nows# ) : 0 = disable 1 = enable smi address relocation: 0 = disable 1 = enable at wait states: 0 = none 1 = one fast reset: 0 = wait for hlt 1 = immediatel y reserved syscfg 31h control register 2 default = 40h master b y te swap: 0 = disable 1 = enable reserved ( ro ) : alwa y s reads 1. reserved: write as 1. d y namic smi relocation: 0 = normal 1 = remap romcs for ec000: see table 4-30 romcs for e8000: see table 4-30 romcs for e4000: see table 4-30 romcs for e0000: see table 4-30 syscfg 32h shadow ram control register 1 default = e4h f0000 access: 0 = dram 1 = rom allow d000 writes: 0 = disable 1 = enable allow e000 writes: 0 = disable 1 = enable d000 block shadow control: 0 = writable 1 = protected e000 block shadow control: 0 = writable 1 = protected refresh on isa bus*: 0 = enable 1 = disable ( hidden refresh mode ) (mvb) * must enable when usin g edo dram. reserved ales in bus conversion: 0 = multiple 1 = sin g le syscfg 33h shadow ram control register 2 default = 00h ec000 read select rom/ram: 0 = rom 1 = shadow ram e8000 read select rom/ram: 0 = rom 1 = shadow ram e4000 read select rom/ram: 0 = rom 1 = shadow ram e0000 read select rom/ram: 0 = rom 1 = shadow ram dc000 read select rom/ram: 0 = rom 1 = shadow ram d8000 read select rom/ram: 0 = rom 1 = shadow ram d4000 read select rom/ram: 0 = rom 1 = shadow ram d0000 read select rom/ram: 0 = rom 1 = shadow ram 82C465MV/mva/mvb opti ? pa g e 158 912-3000-016 revision: 3.0 syscfg 34h dram control register 1 default = 05h - dram banks 0 and 1 confi g uration ( old scheme ) refer to 82c463mv data book for information reserved - dram banks 2 & 3 confi g uration ( old scheme ) syscfg 35h dram control register 2 default = ffh standard dram read wait states: 00 = 3-2-2-2 01 = 4-3-3-3, 1 ws pa g e miss 10 = 4-3-3-3, 0 ws pa g e miss 11 = 5-4-4-4 dram write wait states: 00 = no wait states 01 = 1 wait state 10 = 1 wait state 11 = no wait states, ras# 1/2 clock earl y (mvb) ccs2# ( pin 3 ) strappin g ( ro ) : 0 = 2x cpu 1 = 1x cpu f000 64kb block cacheable? 0 = yes 1 = no global cachin g control: 0 = enable 1 = disable c000 32kb block cacheable? 0 = yes 1 = no syscfg 36h shadow ram control register 3 default = 10h f000 write select destination: 0 = dram 1 = rom don't care for f000 if syscfg 32h [ 7 ] =0 c-d-e000 select destination: 0 = at/rom 1 = dram see table 4-30 c000 write protect: 0 = writable 1 = protected allow c000 writes: 0 = disable 1 = enable cc000 read select rom/ram: 0 = rom 1 = shadow ram c8000 read select rom/ram: 0 = rom 1 = shadow ram c4000 read select rom/ram: 0 = rom 1 = shadow ram c0000 read select rom/ram: 0 = rom 1 = shadow ram syscfg 37h d/e000 control register default = 0fh romcs for dc000: see table 4-30 romcs for d8000: see table 4-30 romcs for d4000: see table 4-30 romcs for d0000: see table 4-30 ec00 16kb block cacheable? 0 = yes 1 = no e800 16kb block cacheable? 0 = yes 1 = no e400 16kb block cacheable? 0 = yes 1 = no e000 16kb block cacheable? 0 = yes 1 = no syscfg 38h block control register 1 default = 80h non-cacheable block 1 ( ncb1 ) size: see table 4-34 romcs for cc000: see table 4-30 romcs for c8000: see table 4-30 romcs for c4000: see table 4-30 romcs for c0000: see table 4-30 ncb1 a24 syscfg 39h block control register 2 default = 00h - non-cacheable block 1 start address a [ 23:16 ] syscfg 3ah block control register 3 default = 80h non-cacheable block 2 ( ncb2 ) size: see table 4-34 reserved ncb2 a24 syscfg 3bh block control register 4 default = 00h - non-cacheable block 2 start address a [ 23:16 ] syscfg 3ch timing control register default = 00h reserved: write as read. reserved: write as read. reserved: write as read. reserved: write as read. reserved: write as read. l2 cache we# dela y (mvb) : 000 = no dela y ... 001 = 1 g ate dela y 110 = 6 g ate dela y s ... 111 = 7 g ate dela y s table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 159 revision: 3.0 syscfg 3dh reserved default = 00h syscfg 3eh dram type select register default = 00h edo dram read wait states: 00 = 3-1-1-1 10 = 4-2-2-2 01 = 3-2-2-2 11 = reserved (mvb) reserved: write as read. bank 4 dram: 0 = standard 1 = edo (mvb) bank 3 dram: 0 = standard 1 = edo (mvb) bank 2 dram: 0 = standard 1 = edo (mvb) bank 1 dram: 0 = standard 1 = edo (mvb) bank 0 dram: 0 = standard 1 = edo (mvb) syscfg 3fh misc. control register default = 00h cpu burst mode: 0 = intel 1 = c y rix linear (mvb) suspend refresh pulse width: 0 = normal 1 = reduced (mvb) four ide drive support: 0 = disable 1 = enable (mvb) cpu burst write support: 0 = disable 1 = enable (mvb) minimum wait states for non-l2 cache s y stems: 0 = 1 ws 1 = 0 ws (mvb) invalidate l1 cache line on writes to wp dram: 0 = disable 1 = enable (mvb) reserved: write as read. reserved: write as read. syscfg 40h pmu control register 1 default = 00h last j ump to reset vector: 0 = ads# 1 = smiads# global timer divide: 0 = divide b y 1 1 = divide b y 4 llowbat polarit y : 0 = active hi 1 = active low lowbat polarit y : 0 = active hi 1 = active low sqwin fre q uenc y : 0 = 32khz 1 = 128khz epmi2 polarit y : 0 = active hi 1 = active low epmi1 polarit y : 0 = active hi 1 = active low rsmrst# select: 0 = disable 1 = enable see fi g ure 4-1 syscfg 41h pmu control register 2 default = 00h doze_0 time-out select: 000 = 2 ms 100 = 128 ms 001 = 4 ms 101 = 512ms 010 = 8 ms 110 = 2s 011 = 32 ms 111 = 8s doze mode s y stem clock speed: 000 = oscclk/1 100 = oscclk/16 001 = oscclk/2 101 = oscclk/3 010 = oscclk/4 110 = reserved 011 = oscclk/8 111 = reserved lcd, dsk, kbd, hdu _access events reset doze mode: 0 = disable 1 = enable doze control select: 0 = hardware 1 = software syscfg 42h clock source register 1 default = 00h clock source for gnr_timer clock source for kbd_timer clock source for dsk_timer clock source for lcd_timer syscfg 43h pmu control register 4 default = 00h lcd_access includes i/o ran g e 3b0h- 3dfh? 0 = yes 1 = no lcd_access includes mem- or y a0000- bffffh? 0 = yes 1 = no lowbat pin sample rate, g enerates pmi each time sampled active: 00 = 32s 01 = 64s 10 = 128s 11 = reserved atclk g enerator source: 0 = fbclkin 1 = atclkin w/ syscfg a0h [ 4 ] = 1 atclk rate selections: 000 = /8 100 = 7.2 mhz 001 = /6 101 = /2 010 = /4 110 = /1 ( /2 if syscfg43h [ 3 ] = 0 ) 011 = /3 111 = stop syscfg 44h lcd_timer register default = 00h time count b y te for lcd_timer - monitors lcd_access. timeout g enerates pmi#8. syscfg 45h dsk_timer register default = 00h time count b y te for dsk_timer - monitors dsk_access. timeout g enerates pmi#9. table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 160 912-3000-016 revision: 3.0 syscfg 46h kbd_timer register default = 00h time count b y te for kbd_timer - monitors kbd_access. timeout g enerates pmi#10. syscfg 47h gnr1_timer register default = 00h time count b y te for gnr1_timer - monitors gnr1_access. timeout g enerates pmi#11. syscfg 48h gnr1 base address register default = 00h gnr1_access base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 49h gnr1 control register default = 00h gnr1 base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable gnr1 mask bits for address a [ 5:1 ] ( i/o ) or a [ 19:15 ] memor y : a '1' in a particular bit means that the correspondin g syscfg 48h [ 4:0 ] is not compared. this is used to determine address block size. syscfg 4ah chip select 0 base address register default = 00h csg0# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 4bh chip select 0 control register default = 00h csg0# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg0# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : a '1' in a particular bit means that the correspondin g syscfg 4ah [ 3:0 ] is not compared. this is used to determine address block size. syscfg 4ch chip select 1 base address register default = 00h csg1# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg 4dh chip select 1 control register default = 00h csg1# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg1# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : a '1' in a particular bit means that the correspondin g bit 4ch [ 3:0 ] is not compared. this is used to determine address block size. syscfg 4eh idle reload event enable register 1 default = 00h csg1_ access: 0 = disable 1 = enable csg0_ access: 0 = disable 1 = enable lpt_ access: 0 = disable 1 = enable reserved gnr1_ access: 0 = disable 1 = enable kbd_ access: 0 = disable 1 = enable dsk_ access: 0 = disable 1 = enable lcd_ access: 0 = disable 1 = enable syscfg 4fh idle_timer register default = 00h time count b y te for idle_timer - monitors selected irqs and epmis. time-out g enerates pmi#4. table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 161 revision: 3.0 syscfg 50h pmu control register 5 default = 00h software start smi: 0 = clear smi 1 = start smi reserved irq8 polarit y : 0 = active low 1 = active hi g h 14.3mhz to ipc: 0 = enable 1 = disable write: 1 to start doze read: doze status 0 = countin g 1 = timed out read y to resume ( ro ) : 0 = not in resume 1 = read y to resume pmu mode ( ro ) : 0 = nothin g pendin g 1 = suspend active ( clear pmi#6 ) start suspend ( wo ) : 1 = enter suspend mode syscfg 51h beeper control register default = 00h general purpose stora g e bits beeper control: 00 = no action 01 = 1khz 10 = off 11 = 2khz syscfg 52h scratchpad register 1 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: data phase information, low b y te (mvb) syscfg 53h scratchpad register 2 default = 00h general purpose stora g e b y te - for cisa confi g uration c y cles: data phase information, hi g h b y te (mvb) syscfg 54h power control latch register 1 default = x0h enable [ 3:0 ] to write latch lines ppwr3-0: 0 = disable 1 = enable read/write data bits for ppwr3-0 - default 0000: 0 = latch output low 1 = latch output hi g h syscfg 55h power control latch register 2 default = xfh enable [ 3:0 ] to write latch lines ppwr7-4: 0 = disable 1 = enable read/write data bits for ppwr7-4 - default 1111: 0 = latch output low 1 = latch output hi g h syscfg 56h pio pin control register default = x0h write mask of syscfg 56h [ 3:0 ] : 0 = disable writes on correspondin g bit [ 3:0 ] 1 = enable bit [ 3:0 ] writes to pio pins read/write data for pio3-0: read: returns value present at pin. write: sets pin value if direction bit is set to 1. syscfg 57h pmu control register 6 default = 00h refresh: 0 = disable 1 = enable intrgrp g en- erates pmi#6: 0 = disable 1 = enable dsk_access includes fdd? 0 = yes 1 = no dsk_access includes hdd? 0 = yes 1 = no pio3 direction: 0 = input 1 = output pio2 direction: 0 = input 1 = output pio1 direction: 0 = input 1 = output pio0 direction: 0 = input 1 = output syscfg 58h pmu event register 1 default = 00h lowbat pmi#3 smi: 00 = disable 11 = enable epmi2 pmi#2 smi: 00 = disable 11 = enable epmi1 pmi#1 smi: 00 = disable 11 = enable llowbat pmi#0 smi: 00 = disable 11 = enable table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 162 912-3000-016 revision: 3.0 syscfg 59h pmu event register 2 default = 00h allow software smi: 0 = disable 1 = enable reload timers on resume? 0 = no 1 = yes resume intrgrp pmi#6, suspend pmi#7 smi: 00 = disable 11 = enable r_timer pmi#5 smi: 00 = disable 11 = enable idle_timer pmi#4 smi: 00 = disable 11 = enable syscfg 5ah pmu event register 3 default = 00h gnr1_timer pmi#11 smi: 00 = disable 11 = enable kbd_timer pmi#10 smi: 00 = disable 11 = enable dsk_timer pmi#9 smi: 00 = disable 11 = enable lcd_timer pmi#8 smi: 00 = disable 11 = enable syscfg 5bh pmu event register 4 default = 00h smi to irq15: 0 = disable 1 = enable global smi control: 0 = allow 1 = mask reserved smi t y pe: 0 = intel 1 = other gnr1 next access pmi#15: 0 = disable 1 = enable kbd next access pmi#14: 0 = disable 1 = enable dsk next access pmi#13: 0 = disable 1 = enable lcd next access pmi#12: 0 = disable 1 = enable syscfg 5ch pmi source register 1 (write 1 to clear) default = 00h pmi#7, suspend: 0 = inactive 1 = active pmi#6, resume or intrgrp: 0 = inactive 1 = active pmi#5, r_timer time-out: 0 = inactive 1 = active pmi#4, idle_tmr time-out: 0 = inactive 1 = active pmi#3, lowbat: 0 = inactive 1 = active pmi#2, epmi2: 0 = inactive 1 = active pmi#1, epmi1: 0 = inactive 1 = active pmi#0, llowbat: 0 = inactive 1 = active syscfg 5dh pmi source register 2 (write 1 to clear) default = 00h pmi#15, gnr1_ access: 0 = inactive 1 = active pmi#14, kbd_access: 0 = inactive 1 = active pmi#13, dsk_access: 0 = inactive 1 = active pmi#12, lcd_access: 0 = inactive 1 = active pmi#11, gnr1_timer: 0 = inactive 1 = active pmi#10, kbd_timer: 0 = inactive 1 = active pmi#9, dsk_timer: 0 = inactive 1 = active pmi#8, lcd_timer: 0 = inactive 1 = active syscfg 5eh clock stretch register default = 00h stretch mem- or y code c y cle: 0 = disable 1 = enable stretch write c y cle: 0 = disable 1 = enable stretch read c y cle: 0 = disable 1 = enable stretch i/o c y cle: 0 = disable 1 = enable stretch mem- or y data c y cle: 0 = disable 1 = enable atclk when not in c y cle: 0 = runs 1 = stopped at clock stretch: 0 = as y nc 1 = s y nc reserved syscfg 5fh pmu control register 7 default = 00h lcd_access includes isa bus video access? 0 = yes 1 = no lcd_access includes vl- bus video access? 0 = no 1 = yes rsmgrp irqs can resume s y stem? 0 = no 1 = yes transitions on ri can resume s y stem? 0 = no 1 = yes number of ri transitions to cause resume syscfg 60h r_timer base count register (ro) default = 00h r_timer initial count table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 163 revision: 3.0 syscfg 61h debounce register default = 00h lowbat, llowbat debounce rate select: 00 = no debounce 01 = 250 s 10 = 8ms 11 = 500ms susp/rsm debounce rate select: 00 = active low, ed g e-tri gg ered pmi 01 = active low, level-controlled pmi 10 = active hi g h, level-sampled pmi in 16ms 11 = active hi g h, level-sampled pmi in 32ms for further decode details, refer to section 4.7.6.1, "suspend/ resume pin" on pa g e 115 reserved stpclk# si g nal: 0 = disable 1 = enable reserved syscfg 62h irq doze register 1 (wo) default = 00h irq13 doze reset: 0 = disable 1 = enable irq8 doze reset: 0 = disable 1 = enable irq7 doze reset: 0 = disable 1 = enable irq12 doze reset: 0 = disable 1 = enable irq5 doze reset: 0 = disable 1 = enable irq4 doze reset: 0 = disable 1 = enable irq3 doze reset: 0 = disable 1 = enable irq0 doze reset: 0 = disable 1 = enable syscfg 63h idle time-out select register 1 default = 00h epmi1 level-tri gg ered: 0 = disable 1 = enable irq13: 0 = disable 1 = enable irq8: 0 = disable 1 = enable irq7: 0 = disable 1 = enable irq5: 0 = disable 1 = enable irq4: 0 = disable 1 = enable irq3: 0 = disable 1 = enable irq0: 0 = disable 1 = enable syscfg 64h intrgrp irq select register 1 default = 00h irq14: 0 = disable 1 = enable irq8: 0 = disable 1 = enable irq7: 0 = disable 1 = enable irq6: 0 = disable 1 = enable irq5: 0 = disable 1 = enable irq4: 0 = disable 1 = enable irq3: 0 = disable 1 = enable irq1: 0 = disable 1 = enable syscfg 65h doze register default = 00h all interrupts to cpu reset doze mode: 0 = disable 1 = enable stpclk # control: 0 = pulse 1 = latch epmi1 doze reset: 0 = disable 1 = enable smi resets doze mode? 0 = no 1 = yes irq1 doze reset: 0 = disable 1 = enable reserved syscfg 66h pmu control register 8 default = 00h suspend refresh: 0 = slow 1 = none ( for self-refresh dram ) suspend kbclk source: 0 = 14mhz/2 1 = 32khz/2 doze t y pe: 0 = slow cpu clock 1 = stop cpu clock assert hold durin g suspend? 0 = yes 1 = no pin 171 function: 0 = pio3 1 = stpgnt# pin 172 function: 0 = pio2 1 = cpuspd pin 173 function: 0 = pio1 1 = nows# cpu clock chan g e proto- col re q uired? 0 = no 1 = yes table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 164 912-3000-016 revision: 3.0 syscfg 67h pmu control register 9 default = 00h reserved refresh rate active or suspend mode: 00 = 15 s ( 30 s in suspend if syscfg a1h [ 6 ] = 0 ) 01 = 30 s 10 = 61 s 11 = 122 s reserved: write as 1. reserved write: select cpu fre q uenc y read: return current operatin g fre q uenc y : 000 = cpuclk/1 100 = cpuclk/16 001 = cpuclk/2 101 = cpuclk/3 010 = cpuclk/4 110 = reserved 011 = cpuclk/8 111 = reserved syscfg 68h clock source register 3 default = 00h r_timer clock source idle_timer clock source resume recover y time: 00 = 8ms 10 = 128ms 01 = 32ms 11 = 30 s i g nored if syscfg beh [ 0 ] = 1 ppwr1-0 auto to gg le: 0 = disable 1 = enable syscfg 69h r_timer register default = 00h time count b y te for r_timer - starts to count after a non zero write to this re g ister. unlike the other timer re g isters, a read from this re g ister returns the current count. timeout g enerates pmi#5. syscfg 6ah rsmgrp irq register 1 default = 00h epmi2 resume: 0 = disable 1 = enable epmi1 resume: 0 = disable 1 = enable irq8 resume: 0 = disable 1 = enable irq7 resume: 0 = disable 1 = enable irq5 resume: 0 = disable 1 = enable irq4 resume: 0 = disable 1 = enable irq3 resume: 0 = disable 1 = enable irq1 resume: 0 = disable 1 = enable syscfg 6bh resume source register default = 00h reserved: write as read. pin 135 function: 0 = flush# 1 = smirdy# reserved: write as read. reserved: write as read. cisa sel#/ atb# low caused resume ( ro ) ? 0 = no 1 = yes (mvb) susp/rsm caused resume ( ro ) ? 0 = no 1 = yes rsmgrp caused resume ( ro ) ? 0 = no 1 = yes ri caused resume ( ro ) ? 0 = no 1 = yes syscfg 6ch scratchpad register 3 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, low b y te (mvb) syscfg 6dh scratchpad register 4 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 1 information, hi g h b y te (mvb) syscfg 6eh scratchpad register 5 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, low b y te (mvb) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 165 revision: 3.0 syscfg 6fh scratchpad register 6 default = 00h general purpose stora g e b y te: - for cisa confi g uration c y cles: address phase 2 information, hi g h b y te (mvb) syscfg 70h gnr1 control register 2 default = 00h gnr1_access base address: -a [ 13:6 ] for memor y watchdo g -a [ 15:10 ] for i/o ( ri g ht-ali g ned ) (mva) syscfg 71h gnr1 control register 3 default = 00h gnr1_access mask bits: - mask for a [ 13:6 ] for memor y watchdo g - mask for a [ 15:10 ] for i/o ( ri g ht-ali g ned ) (mva) syscfg 72h gnr1 base address register 4 default = 00h gnr1_access base address (mva and mvb) : -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o *in mvb, if syscfg aeh [ 6 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 6 ] = 1. gnr1_access mask bits (mva and mvb) : - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o *in mvb, if syscfg aeh [ 6 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 6 ] = 1. syscfg 73h gnr1 control register 2 default = 00h gnr2_access base address: -a [ 13:6 ] for memor y watchdo g -a [ 15:10 ] for i/o ( ri g ht-ali g ned ) (mva) syscfg 74h gnr1 control register 3 default = 00h gnr2_access mask bits: - mask for a [ 13:6 ] for memor y watchdo g - mask for a [ 15:10 ] for i/o ( ri g ht-ali g ned ) (mva) syscfg 75h gnr1 base address register 4 default = 00h gnr2_access base address (mva and mvb) : -a [ 5:2 ] for memor y watchdo g * -i g nored for i/o *in mvb, if syscfg aeh [ 7 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 7 ] = 1. gnr2_access mask bits (mva and mvb) : - mask for a [ 5:2 ] for memor y watchdo g * - mask for a [ 9:6 ] for i/o *in mvb, if syscfg aeh [ 7 ] = 0. for a [ 31 ] +x+a [ 25 ] + [ a24 ] if syscfg aeh [ 7 ] = 1. syscfg 76h doze reload select register 1 default = 00h lcd_access: 0 = doze_0 1 = doze_1 (mva) kbd_access: 0 = doze_0 1 = doze_1 (mva) dsk_access: 0 = doze_0 1 = doze_1 (mva) hdu_access: 0 = doze_0 1 = doze_1 (mva) com1&2_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) lpt_access: 0 = doze_0 1 = doze_1 default = 1 (mva) gnr1_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) gnr2_ access: 0 = doze_0 1 = doze_1 default = 1 (mva) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 166 912-3000-016 revision: 3.0 syscfg 77h doze reload select register 2 default = 00h irq8: 0 = doze_0 1 = doze_1 (mva) irq7: 0 = doze_0 1 = doze_1 (mva) irq6: 0 = doze_0 1 = doze_1 (mva) irq5: 0 = doze_0 1 = doze_1 (mva) irq4: 0 = doze_0 1 = doze_1 (mva) irq3: 0 = doze_0 1 = doze_1 (mva) irq1: 0 = doze_0 1 = doze_1 (mva) irq0: 0 = doze_0 1 = doze_1 (mva) syscfg 78h doze reload select register 3 default = 00h ldev#: 0 = doze_0 1 = doze_1 (mva) irq15: 0 = doze_0 1 = doze_1 (mva) irq14: 0 = doze_0 1 = doze_1 (mva) irq13: 0 = doze_0 1 = doze_1 (mva) irq12: 0 = doze_0 1 = doze_1 (mva) irq11: 0 = doze_0 1 = doze_1 (mva) irq10: 0 = doze_0 1 = doze_1 (mva) irq9: 0 = doze_0 1 = doze_1 (mva) syscfg 79h pmu control register 11 default = 00h doze_1 time-out select (mva) : 000 = no dela y ( default ) 100 = 64ms 001 = 1ms 101 = 256 ms 010 = 4ms 110 = 1s 011 = 16ms 111 = 4s smi resets doze mode if clock is stopped inside smm? 0 = no 1 = yes (mva) pin 172 function: 0 = pio2 or cpuspd 1 = buffer enable pin sabufen# (mva) fast lo g ic functionalit y level: 00 = full y functional 01 = do not inhibit kbdcs# 10 = also: disable reset from 060/ 064h 11 = also: redefine pin 179 as kbcrstin (mva) kbclk/ kbclk2 control: 0 = normal operation 1 = stopped in low state (mva) syscfg 7ah-7fh reserved default = 00h syscfg 80h interrupt controller 1 shadow register icw1 default = xxh syscfg 81h interrupt controller 1 shadow register icw2 default = xxh syscfg 82h interrupt controller 1 shadow register icw3 default = xxh syscfg 83h interrupt controller 1 shadow register icw4 default = xxh syscfg 84h dma in-progress register (ro) default = xxh channel 7 dma in pro g ress: 0 = no 1 = possibl y channel 6 dma in pro g ress: 0 = no 1 = possibl y channel 5 dma in pro g ress: 0 = no 1 = possibl y dmac2 b y te pointer flip- flop ( ro ) . 0 = cleared 1 = set (mva) channel 3 dma in pro g ress: 0 = no 1 = possibl y channel 2 dma in pro g ress: 0 = no 1 = possibl y channel 1 dma in pro g ress: 0 = no 1 = possibl y channel 0 dma in pro g ress: 0 = no 1 = possibl y syscfg 85h interrupt controller 1 shadow register ocw1 default = xxh syscfg 86h interrupt controller 1 shadow register ocw2 default = xxh syscfg 87h reserved default = 00h syscfg 88h interrupt controller 2 shadow register icw1 default = xxh syscfg 89h interrupt controller 2 shadow register icw2 default = xxh syscfg 8ah interrupt controller 2 shadow register icw3 default = xxh syscfg 8bh interrupt controller 2 shadow register icw4 default = xxh syscfg 8ch reserved default = 00h table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 167 revision: 3.0 syscfg 8dh interrupt controller 2 shadow register ocw1 default = xxh syscfg 8eh interrupt controller 2 shadow register ocw2 default = xxh syscfg 8fh reserved default = 00h syscfg 90h timer channel 0 count low byte: a[7:0] default = xxh syscfg 91h timer channel 0 count high byte: a[15:8] default = xxh syscfg 92h timer channel 1 count low byte: a[7:0] default = xxh syscfg 93h timer channel 1 count high byte: a[15:8] default = xxh syscfg 94h timer channel 2 count low byte: a[7:0] default = xxh syscfg 95h timer channel 2 count high byte: a[15:8] default = xxh syscfg 96h write counter high/low byte latch default = xxh unused unused channel 2 read lsb to gg le bit channel 1 read lsb to gg le bit channel 0 read lsb to gg le bit channel 2 write lsb to gg le bit channel 1 write lsb to gg le bit channel 0 write lsb to gg le bit syscfg 97h reserved default = 00h syscfg 98h rtc index shadow register (ro) default = 00h nmi enable settin g - cmos ram index last written syscfg 99h-9ah reserved default = 00h syscfg 9bh 3f2h+3f7h shadow register default = 00h shadows 3f2h [ 7 ] mode select bit (mva) shadows 3f7h [ 1 ] disk t y pe bit 1 (mva) shadows 3f2h [ 5 ] drive 2 motor bit (mva) shadows 3f2h [ 4 ] drive 1 motor bit (mva) shadows 3f2h [ 3 ] dma enable bit (mva) shadows 3f2h [ 2 ] soft reset bit (mva) shadows 3f7h [ 0 ] disk t y pe bit 0 (mva) shadows 3f2h [ 0 ] drive select bit (mva) syscfg bch 372h+377h shadow register default = 00h shadows 372h [ 7 ] mode select bit (mva) shadows 377h [ 1 ] disk t y pe bit 1 (mva) shadows 372h [ 5 ] drive 2 motor bit (mva) shadows 372h [ 4 ] drive 1 motor bit (mva) shadows 372h [ 3 ] dma enable bit (mva) shadows 372h [ 2 ] soft reset bit (mva) shadows 377h [ 0 ] disk t y pe bit 0 (mva) shadows 372h [ 0 ] drive select bit (mva) syscfg 9dh-9eh reserved default = 00h syscfg 9fh port 064h shadow register default = 00h - shadows i/o writes to port 064h bits [ 7:0 ] , re g ardless of whether kbdcs# is inhibited. in this wa y , when an smi occurs between a port 064h write and the subse q uent write to port 060h, smm code can access the ke y board controller as needed and then simpl y restore the port 064h value j ust before leavin g smm. (mva) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 168 912-3000-016 revision: 3.0 syscfg a0h feature control register 1 default = 00h internal i/o address decodin g : 0 = 10-bit 1 = 16-bit automatic internal resistors: 0 = disable 1 = enable enable local bus master support: 0 = pio0 and dack2# 1 = lreq# and lgnt# pin 172 function: 0 = pio2 ( or cpuspd ) 1 = atclkin enable alterna- tive dackmux interface: 0 = disable 1 = enable see table 3-5 allow sreset in smm: 0 = enable 1 = disable cpu cache operation select: 0 = standard 1 = l1 write- back dram mappin g : 0 = disable 1 = enable syscfg a1h feature control register 2 default = 00h port 060/4 gate a20 ( ro ) : in mvb, port 060/4 a20m# bit read: return current value; write: to gg le a20m# settin g suspend refresh pulse g eneration: 0 = wide 1 = ~100ns pin 88 - for epmi3-4: 0 = drq2 1 = epmmux heav y -dut y memor y bus drive: 0 = disable 1 = enable heav y -dut y isa bus drive: 0 = disable 1 = enable emer g enc y overtemp sense: 0 = disable 1 = enable f000 shadow test: 0 = read or write 1 = read and write epmi1-2 status latch: 0 = d y namic 1 = latched syscfg a2h irq doze register 2 (wo) default = 00h local bus i/o access doze reset: 0 = disable 1 = enable (mva) local bus mem- or y access doze reset: 0 = disable 1 = enable (mva) irq15 doze reset: 0 = disable 1 = enable irq14 doze reset: 0 = disable 1 = enable irq11 doze reset: 0= disable 1= enable irq10 doze reset: 0 = disable 1 = enable irq9 doze reset: 0 = disable 1 = enable irq6 doze reset: 0 = disable 1 = enable syscfg a3h idle time-out select register 2 default = 00h irq15: 0 = disable 1 = enable irq14: 0 = disable 1 = enable irq12: 0 = disable 1 = enable irq11: 0 = disable 1 = enable irq10: 0 = disable 1 = enable irq9: 0 = disable 1 = enable irq6: 0 = disable 1 = enable irq1: 0 = disable 1 = enable syscfg a4h intrgrp irq select register 2 default = 00h test bit: write as 0. irq15: 0 = disable 1 = enable irq13: 0 = disable 1 = enable irq12: 0 = disable 1 = enable irq11: 0 = disable 1 = enable irq10: 0 = disable 1 = enable irq9: 0 = disable 1 = enable irq0: 0 = disable 1 = enable syscfg a5h thermal management register 1 default = 00h thermal mana g ement: 0 = disable 1 = enable e q uilibrium level ( eql6:0 ) : - this count corresponds to e q uilibrium operation. if the cpu activit y counter exceeds eql, eql is simpl y subtracted from the upper activit y count b y te and samplin g continues. if the count is below eql, the count is cleared. syscfg a6h thermal management register 2 default = 00h overtemp limit ( otl7:0 ) : - this count corresponds to an over-temperature situation. if the cpu activit y counter exceeds otl, the 82C465MV en g a g es cool-down clockin g . table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 169 revision: 3.0 syscfg a7h thermal management register 3 default = 00h cpu efficienc y ( cpue1:0 ) : 00 = low power 01 = moderate 10 = hi g h 11 = ver y hi g h cool-down holdoff ( cdho1:0 ) : 00 = 32s 01 = 64s 10 = 128s 11 = 256s cool-down clock rate ( cdcr1:0 ) : 00 = /2 01 = /3 10 = /4 11 = /8 cool-down time-out ( cdto1:0 ) : 00 = 2x cdho 01 = 3x 10 = 4x 11 = 5x syscfg a8h dram bank select register 1 default = 00h bank 1 t y pe: 0 = s y m 1 = as y m bank 1 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb bank 0 t y pe: 0 = s y m 1 = as y m bank 0 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb syscfg a9h dram bank select register 2 default = 00h bank 3 t y pe: 0 = s y m 1 = as y m bank 3 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb bank 2 t y pe: 0 = s y m 1 = as y m bank 2 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb syscfg aah dram bank select register 3 default = 00h reserved bank 4 t y pe: 0 = s y m 1 = as y m bank 4 memor y size: 000 = not installed 100 = 8mb 001 = 1mb 101 = 16mb 010 = 2mb 110 = 32mb 011 = 4mb 111 = 64mb syscfg abh pmu control register 3 default = x0h enable [ 3:0 ] to write latch lines ppwr11-8: 0 = disable 1 = enable read/write data bits for ppwr11-8 - default 0000: 0 = latch output low 1 = latch output hi g h syscfg ach ide interface configuration register default = 00h chipset input clock fre q uenc y : 00 = 50mhz 01 = 40mhz 10 = 33mhz 11 = 20/25mhz ide command pulse duration: 00 = 600ns 01 = 383ns 10 = 240ns 11 = 180ns ide interface: 0 = disable 1 = enable ide port address select: 0 = 1f0-7h, 3f6-7h 1 = 170-7h, 376-7h 3f7h [ 6:0 ] source: 0 = local ide 1 = isa bus reserved syscfg adh feature control register 3 default = 00h i g nore unfinished ldev# c y cles: 0 = wait 1 = i g nore generate cpurst immediatel y ? 0 = no 1 = yes (mva) cpu power state in suspend: 0 = powered 1 = 0 volt pin 130 in 386 mode: 0 = ga20 1 = a20m# sreset operation: 0 = normal 1 = to gg le on resume pin 80 in 386 mode: 0 = npint 1 = dack2# coprocessor reco g nition: 0 = enable 1 = override rdyi# input: 0 = s y nchro- nized to rdy# 1 = direct table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 170 912-3000-016 revision: 3.0 syscfg aeh gnr_access feature register default = 03h gnr2 memor y decodin g : 0 = a [ 5:2 ] 1 = a [ 31:24 ] (mvb) gnr1 memor y decodin g : 0 = a [ 5:2 ] 1 = a [ 31:24 ] (mvb) gnr2 c y cle decode t y pe: 0 = i/o 1 = memor y gnr1 c y cle decode t y pe: 0 = i/o 1 = memor y gnr2 base address: a0 ( i/o ) a14 ( memor y) gnr1 base address: a0 ( i/o ) a14 ( memor y) gnr2 mask bit: a0 ( i/o ) a14 ( memor y) gnr1 mask bit: a0 ( i/o ) a14 ( memor y) syscfg afh smbase register default = 34h smm se g ment to be mapped to b000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 3h ) smm se g ment to be mapped to a000h: 0 = 0:0 1 = 1000:0h ... 9 = 9000:0h ( a-f ille g al ) ( defaults to 4h ) syscfg b0h stop clock delay register default = 00h stop clock dela y : 0 = disable 1 = enable stop clock dela y time base: 0 = 32khz/4 ( ~122 us ) 1 = fbclk/4 dela y count: - this value multiplies the time base period selected in bit [ 6 ] . there is an additional 6 fbclk dela y for all selections, even no dela y . sample approximate dela y s based on 32khz/25mhz selections: 000000 = no dela y 000011 = 366 s/480ns 001001 = 1.1ms/1.44 s 000001 = 122us/160ns ... ... 000010 = 244 s/320ns 001000 = 976 s/1.28 s 111111 = 7.7ms/10.0 s syscfg b1h rsmgrp irq register 2 default = 00h epmi4 resume: 0 = disable 1 = enable epmi3 resume: 0 = disable 1 = enable irq15 resume: 0 = disable 1 = enable irq14 resume: 0 = disable 1 = enable irq12 resume: 0 = disable 1 = enable irq11 resume: 0 = disable 1 = enable irq10 resume: 0 = disable 1 = enable irq9 resume: 0 = disable 1 = enable syscfg b2h clock source register 2 default = 00h clock source for hdu_timer clock source for com2_timer clock source for com1_timer clock source for gnr2_timer syscfg b3h chip select cycle type register default = 00h csg3# rom width: 0 = 8-bit 1 = 16-bit csg2# rom width: 0 = 8-bit 1 = 16-bit csg1# rom width: 0 = 8-bit 1 = 16-bit csg0# rom width: 0 = 8-bit 1 = 16-bit csg3# c y cle t y pe: 0 = i/o 1 = romcs csg2# c y cle t y pe: 0 = i/o 1 = romcs csg1# c y cle t y pe: 0 = i/o 1 = romcs csg0# c y cle t y pe: 0 = i/o 1 = romcs syscfg b4h hdu_timer register default = 00h time count b y te for hdu_timer - monitors hdu_access. timeout g enerates pmi#19. syscfg b5h com1_timer register default = 00h time count b y te for com1_timer - monitors com1_access. timeout g enerates pmi#17. syscfg b6h com2_timer register default = 00h time count b y te for com2_timer - monitors com2_access. timeout g enerates pmi#18. syscfg b7h gnr2_timer register default = 00h time count b y te for gnr2_timer - monitors gnr2_access. timeout g enerates pmi#16. table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 171 revision: 3.0 syscfg b8h gnr2 base address register default = 00h gnr2_access base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg b9h gnr2 control register default = 00h gnr2 base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable gnr2 mask bits for address a [ 5:1 ] ( i/o ) or a [ 19:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg b8h [ 4:0 ] is not com- pared. this is used to determine address block size. syscfg bah chip select 2 base address register default = 00h csg2# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg bbh chip select 2 control register default = 00h csg2# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg2# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg bah [ 3:0 ] is not compared. this is used to determine address block size. syscfg bch chip select 3 base address register default = 00h csg3# base address: -a [ 8:1 ] ( i/o ) -a [ 22:15 ] ( memor y) syscfg bdh chip select 3 control register default = 00h csg3# base address: a9 ( i/o ) a23 ( memor y) write decode: 0 = disable 1 = enable read decode: 0 = disable 1 = enable chip select active: 0 = w/cmd 1 = before ale csg3# mask bits for address a [ 4:1 ] ( i/o ) or a [ 18:15 ] memor y : - a '1' in a particular bit means that the correspondin g syscfg bch [ 3:0 ] is not compared. this is used to determine address block size. syscfg beh idle reload event enable register 2 default = 00h csg3_ access: 0 = disable 1 = enable csg2_ access: 0 = disable 1 = enable com2_ access: 0 = disable 1 = enable com1_ access: 0 = disable 1 = enable gnr2_ access: 0 = disable 1 = enable hdu_ access: 0 = disable 1 = enable reserved override syscfg 68h [ 3:2 ] : 0 = no 1 = recover time 1s syscfg bfh chip select granularity register default = 0fh csg3# base address: a0 ( i/o ) a14 ( memor y) csg2# base address: a0 ( i/o ) a14 ( memor y) csg1# base address: a0 ( i/o ) a14 ( memor y) csg0# base address: a0 ( i/o ) a14 ( memor y) csg3# mask bit: a0 ( i/o ) a14 ( memor y) csg2# mask bit: a0 ( i/o ) a14 ( memor y) csg1# mask bit: a0 ( i/o ) a14 ( memor y) csg0# mask bit: a0 ( i/o ) a14 ( memor y) syscfg c0h-cfh reserved default = 00h table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 172 912-3000-016 revision: 3.0 syscfg d0h l2 cache control register 1 default = c0h l2 cache ccs0-3# deassert: 0 = stop g rant and sus- pend 1 = also between accesses l2 cache con- trols suspend state: 0 = tristate 1 = driven l2 cache en g a g e: 0 = disable 1 = enable cache size: 00 = 64kb 01 = 128kb 10 = 256kb 11 = reserved l2 cache write wait state: 0 = 1 ws 1 = no ws l2 cache read burst wait state control: 0 = x-1-1-1 1 = x-2-2-2 l2 cache first read wait state control: 0 = 3-x-x-x 1 = 2-x-x-x syscfg d1h l2 cache control register 2 default = 41h l1 cache hitm# sensin g after eads#: 0 = 2nd clock 1 = 3rd clock ads# samplin g : 0 = sample on ads# low 1 = latch ads#, sam- ple on next c y cle l2 ta g ram size: 0 = 8-bit 1 = 7-bit (mva) l2 cache arran g ement: 0 = two banks 1 = one bank (mva) ec000- effffh l2 cacheable? 0 = no 1 = yes e8000- ebfffh l2 cacheable? 0 = no 1 = yes e4000-e7fffh l2 cacheable? 0 = no 1 = yes e0000-e3fffh l2 cacheable? 0 = no 1 = yes syscfg d2h l2 cache control register 3 default = 00h dc000- dffffh l2 cacheable? 0 = no 1 = yes d8000- dbfffh l2 cacheable? 0 = no 1 = yes d4000- d7fffh l2 cacheable? 0 = no 1 = yes d0000- d3fffh l2 cacheable? 0 = no 1 = yes cc000- cffffh l2 cacheable? 0 = no 1 = yes c8000- cbfffh l2 cacheable? 0 = no 1 = yes c4000- c7fffh l2 cacheable? 0 = no 1 = yes c0000- c3fffh l2 cacheable? 0 = no 1 = yes syscfg d3h asym. dram select register default = 00h se g ment for smm data reads: 0 = a000h 1 = smbase (mva) se g ment for smm data writes: 0 = a000h 1 = smbase (mva) cache flush on smi entr y : 0 = enable 1 = disable (mva) bank 4 as y m t y pe: 0 = 11x9 1 = 12x8 bank 3 as y m t y pe: 0 = 11x9 1 = 12x8 bank 2 as y m t y pe: 0 = 11x9 1 = 12x8 bank 1 as y m t y pe: 0 = 11x9 1 = 12x8 bank 0 as y m t y pe: 0 = 11x9 1 = 12x8 syscfg d4h resistor control register 1 default = 00h ca31, ca [ 25:2 ] , be [ 3:0 ] # pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved cd [ 31:0 ] pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved m/io#, d/c#, w/r# pull-down resistor control: 00 = automatic 01 = alwa y s enabled 10 = alwa y s disabled 11 = reserved reserved redefine pin 189: 0 = boff# 1 = lclk (mva) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 173 revision: 3.0 syscfg d5h resistor control register 2 default = 00h dackmux control durin g suspend: 00 = pull resistor-e q uipped lines low, drive others low 01 = tristate all lines ( 463mv mode ) 10 = drive 100b on dackmux2-0 11 = reserved ferr# pull-up resistor control: 0 = alwa y s enabled 1 = alwa y s disabled reserved generate boff# ( ahold ) on next access trap: 0 = disable 1 = enable syscfg d6h pmu control register 10 default = 00h dsk_access: 0 = 3f5h onl y 1 = all fdc ports ( 3f2,4,5,7h and 372,4,5,7h ) (mva) dma trap pmi#28 smi: 0 = disable 1 = enable (mva) dmac1 b y te pointer flip-flop ( ro ) : 0 = cleared 1 = set (mva) hitm# source: 0 = d/c# 1 = pin 135 (mva) local bus dma ldev# samplin g : 0 = normal 1 = sample one clock sooner (mva) i/o port access trapped ( ro ) : 0 = i/o read 1 = i/o write (mva) access trap bit a9 ( ro ) (mva) access trap bit a8 ( ro ) (mva) syscfg d7h access port address register default = 00h access trap address bits a [ 7:0 ] : - these bits, alon g with a [ 9:8 ] in bits d6h [ 1:0 ] , provide the 10-bit i/o address of the port access that caused the smi trap. syscfg d6h [ 2 ] indicates whether an i/o read or i/o write access was trapped. (mva) syscfg d8h pmu event register 5 default = 00h hdu_timer pmi#19 hdu_access pmi#23 smi: 00 = disable 11 = enable com2_timer pmi#18 com2_access pmi#22 smi: 00 = disable 11 = enable com1_timer pmi#17 com1_access pmi#21 smi: 00 = disable 11 = enable gnr2_timer pmi#16 gnr2_access pmi#20 smi: 00 = disable 11 = enable syscfg d9h pmu event register 6 default = 00h doze_timer pmi#27 smi: 00 = disable 01 = enable doze_0 (mva) 10 = enable doze_1 (mva) 11 = enable both ri pmi#26 smi: 00 = disable 11 = enable epmi4 pmi#25 smi: 00 = disable 11 = enable epmi3 pmi#24 smi: 00 = disable 11 = enable syscfg dah power mgt. event status register (ro) default = 00h reserved: mask when readin g reserved: mask when readin g lowbat state: 0 = inactive 1 = active llowbat state: 0 = inactive 1 = active epmi4 state: 0 = inactive 1 = active epmi3 state: 0 = inactive 1 = active epmi2 state: 0 = inactive 1 = active epmi1 state: 0 = inactive 1 = active table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 174 912-3000-016 revision: 3.0 syscfg dbh next access event generation register 2 default = 00h i/o blockin g control: 0 = block i/o next access 1 = unblock smi on cool- down clockin g entr y /exit pmi#25 smi: 0 = disable 1 = enable external epmi4 pin polarit y : 0 = active hi 1 = active low external epmi3 pin polarit y : 0 = active hi 1 = active low hdu_ access pmi#23 on next access? 0 = no 1 = yes com2_ access pmi#22 on next access? 0 = no 1 = yes com1_ access pmi#21 on next access? 0 = no 1 = yes gnr2_ access pmi#20 on next access? 0 = no 1 = yes syscfg dch pmu smi source register 3 (write 1 to clear) default = 00h pmi#23, hdu_ access: 0 = inactive 1 = active pmi#22, com2_ access: 0 = inactive 1 = active pmi#21, com1_ access: 0 = inactive 1 = active pmi#20, gnr2_ access: 0 = inactive 1 = active pmi#19, hdu_ timer: 0 = inactive 1 = active pmi#18, com2_ timer: 0 = inactive 1 = active pmi#17, com1_ timer: 0 = inactive 1 = active pmi#16, gnr2_ timer: 0 = inactive 1 = active syscfg ddh pmu smi source register 4 default = 00h reserved pmi#28, dma: 0 = clear 1 = active (mva) pmi#27, doze_timer: 0 = clear 1 = active pmi#26, ri: 0 = clear 1 = active pmi#25, epmi4 pin/ cool-down clockin g : 0 = clear 1 = active pmi#24, epmi3 pin: 0 = clear 1 = active syscfg deh current access event generation register default = 00h hdu_ access pmi#23 on current access? 0 = no 1 = yes com2_ access pmi#22 on current access? 0 = no 1 = yes com1_ access pmi#21 on current access? 0 = no 1 = yes gnr2_ access pmi#20 on current access? 0 = no 1 = yes gnr1_ access pmi#15 on current access? 0 = no 1 = yes kbd_ access pmi#14 on current access? 0 = no 1 = yes dsk_ access pmi#13 on current access? 0 = no 1 = yes lcd_ access pmi#12 on current access? 0 = no 1 = yes syscfg dfh activity tracking register default = 00h hdu_ access activit y ? 0 = no 1 = yes com2_ access activit y ? 0 = no 1 = yes com1_ access activit y ? 0 = no 1 = yes gnr2_ access activit y ? 0 = no 1 = yes gnr1_ access activit y ? 0 = no 1 = yes kbd_ access activit y ? 0 = no 1 = yes dsk_ access activit y ? 0 = no 1 = yes lcd_ access activit y ? 0 = no 1 = yes syscfg e0h-e9h reserved default = 00h table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 175 revision: 3.0 syscfg eah pmu source register 5 (mvb) default = 00h irq/drq driveback trap pmi#36: 0 = inactive 1 = active write 1 to clear reserved: write as read. syscfg ebh-f7h reserved default = 00h syscfg f8h compact isa control register 1 (mvb) default = 00h inhibit mrd# and mwr# if sel# asserted on memor y c y cle? 0 = no 1 = yes inhibit mrd# and mwr# if sel# asserted on dma c y cle? 0 = no 1 = yes inhibit iord# and iowr# if sel# asserted on i/o c y cle? 0 = no 1 = yes irq15 assi g nment: 0 = irq15 1 = ri reserved fast cisa memor y c y cle: 0 = disable ( isa# = 0 ) 1 = enable ( isa#=1 ) pin 78 function: 0 = ras4# 1 = cdir compact isa interface ( reas- si g ns pins 173, 186 ) : 0 = disable 1 = enable syscfg f9h compact isa control register 2 (mvb) default = 00h spkd si g nal drivin g : 0 = alwa y s, per at spec. 1 = s y nchro- nousl y , per cisa spec. end-of-interrupt hold: dela y s 8259 reco g nition of eoi command to prevent false inter- rupts. 00 = none 01 = 1 atclk 10 = 2 atclks 11 = 3 atclks stop clock count bits cc [ 2:0 ] : stop clock c y cle indication to cisa devices of how man y atclks to expect before the clock will stop. 000 = reserved 001 = 1 atclk ( default ) ... 111 = 7 atclks generate cisa stop clock c y cle ( if not alread y stopped ) : 00 = never 01 = on stpclk# c y cles to the cpu ( hardware ) 10 = immediatel y ( software ) 11 = reserved syscfg fah compact isa control register 3 (mvb) default = 00h reserved: write as read. reassi g n epmi3 as ri? 0 = no 1 = yes use in case ri is assi g ned as sel#/atb# reassi g n epmi4 as iochck#? 0 = no 1 = yes use in case iochck# is assi g ned as kbcrstin resume from suspend on sel#/atb# low: 0 = disable 1 = enable cmd# state durin g suspend: 0 = driven inac- tive ( hi g h ) 1 = driven low driveback c y cle handlin g : 0 = pass drqs and irqs 1 = latch info and g ener- ate smi confi g uration c y cle g enera- tion: 0 = no action 1 = run c y cle usin g scratchpad syscfg fbh reserved default = 00h syscfg fch scratchpad register 7 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: irq phase information, low b y te ( ro ) (mvb) syscfg fdh scratchpad register 8 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: irq phase information, hi g h b y te ( ro ) (mvb) syscfg feh scratchpad register 9 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: drq phase information, low b y te ( ro ) (mvb) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? pa g e 176 912-3000-016 revision: 3.0 syscfg ffh scratchpad register 10 default = 00h general purpose stora g e b y te: - for cisa driveback c y cle: drq phase information, hi g h b y te ( ro ) (mvb) table 5-1 syscfg register space 76543210 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 177 revision: 3.0 6.0 electrical ratings stresses above those listed in the followin g tables ma y cause permanent dama g e to the device. these are stress ratin g s onl y and functional operation of the device at these or an y other conditions above those indicated in the operational sections of this specification are not implied. 6.1 absolute maximum ratings 6.2 5.0v dc characteristics: ta = 0c to +70c, vdds = 5.0v 5% note: assumes controlled leaka g e currents. symbol description min max units vdd/vdds operatin g volta g e3.06.5v vih input hi g h volta g e vdds + 0.3 v vil input low volta g e C0.3 v ta ambient temperature 0 70 c symbol description min max units vih input hi g h volta g e ttl level 2.0 v cmos level 2.0v v vt+ schmitt-tri gg er input volta g e ( ttl ) positive goin g threshold 2.2 v vtC schmitt-tri gg er input volta g e ( ttl ) ne g ative goin g threshold 0.8 v vil input low volta g e ttl level 0.8 v cmos level 0.8 v voh output hi g h volta g e ( at rated drive current ) cmos level 2.4 v vol output low volta g e ( at rated drive current ) cmos level 0.45 v iih input leaka g e current , vin = vdds C10 10 a iil input leaka g e current , vin = gnd C10 10 a ioz tristate leaka g e current 0.45v < vout < vdds C10 10 a icc operatin g current 33mhz , on mode ( note ) 100 ma suspend mode ( note ) 100 a 82C465MV/mva/mvb opti ? pa g e 178 912-3000-016 revision: 3.0 6.3 3.3v dc characteristics: ta = 0c to +70c, vdd = 3.3v 5% note: assumes controlled leaka g e currents. 6.4 ac characteristics symbol description min max units vih input hi g h volta g e2.0v vt+ schmitt-tri gg er input volta g e ( ttl ) positive goin g threshold 2.2 v vtC schmitt-tri gg er input volta g e ( ttl ) ne g ative goin g threshold 0.8 v vil input low volta g e0.8v voh output hi g h volta g e ( at rated drive current ) 2.4 v vol output low volta g e ( at rated drive current ) 0.45 v iih input leaka g e current , vin = vdd C10 10 a iil input leaka g e current , vin = gnd C10 10 a ioz tristate leaka g e current 0.45v < vout < vdd C10 10 a icc operatin g current 33mhz , on mode ( note ) 50 ma suspend mode ( note ) 40 a symbol description min max units cin input capacitance 10 pf cout output capacitance 10 pf cio i/o capacitance 12 pf 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 179 revision: 3.0 6.5 timing characteristics: cpu interface = 3.3v, all other interfaces = 5.0v sym. parameter min typ max unit 6.5.1 cache timing t1 cpu bus definition valid to beoe#/booe# active dela y ( for 2-x-x-x leadoff c y cles onl y) 10 20 ns t2 clk risin g ed g e to beoe#/booe# active dela y 520ns t3 clk risin g ed g e to beoe#/booe# inactive dela y 20 ns t4 clk risin g ed g e to brdy# active dela y 515ns t5 clk risin g ed g e to brdy# inactive dela y 515ns t7 clk fallin g ed g e to ecawe#/ocawe# active dela y 15 ns t8 clk fallin g ed g e to ecawe#/ocawe# inactive dela y ( 0 wait state write , dirt y) 20 ns t9 clk fallin g ed g e to ecawe#/ocawe# inactive dela y ( 0 wait state write , not dirt y, or 1 wait state write , dirt y) 16 ns t9a clk risin g ed g e to ecawe#/ocawe# active dela y with dram at speed of 3-2-2-2 20 ns t9b clk fallin g ed g e to ecawe#/ocawe# inactive dela y with dram at speed of 3-2-2-2 17 ns t10 clk fallin g ed g e to tagwe# active dela y ( for updatin g dirty bit ) 15 ns t11 clk fallin g ed g e to tagwe# inactive dela y ( for updatin g dirty bit ) 515ns t12 clk risin g ed g e to brdy# active dela y ( for cache write c y cles ) 520ns t13 clk risin g ed g e to brdy# inactive dela y ( for cache write c y cles ) 510ns t14 clk risin g ed g e to tagwe# active dela y ( for updatin g tag ) 515ns t15 clk risin g ed g e to tagwe# inactive dela y ( for updatin g tag ) 515ns t16 cpu bus definition valid to eca3/eca2 valid dela y 16 ns t17 clk risin g ed g e to eca3/eca2 invalid dela y 10 ns t161 hitm# si g nal setup time 10 ns t162 ads# active to hold active dela y 10 30 ns t167 fbclk risin g ed g e to eads# active dela y 525ns t168 fbclk risin g ed g e to eads# inactive dela y 525ns 6.5.2 dram timing t18 clk risin g ed g e to cas# active dela y 520ns t19 clk risin g ed g e to cas# inactive dela y 520ns t20 clk fallin g ed g e to cas# active dela y ( for 3-2-2-2 cache burst c y cles onl y) 520ns 82C465MV/mva/mvb opti ? pa g e 180 912-3000-016 revision: 3.0 t21 clk risin g ed g e to cas# inactive dela y ( for 3-2-2-2 cache burst c y cles onl y) 15 ns t22 clk risin g ed g e to ras# inactive dela y 520ns t23 clk risin g ed g e to ras# active dela y 520ns t24 a clk risin g ed g e to column address valid dela y 515ns t25 clk risin g ed g e to row address hold time 8 30 ns t26 clk risin g ed g e to dwe# active dela y 51530ns t27 clk risin g ed g e to dwe# inactive dela y 51530ns t29 ras# prechar g e time 80 ns t30 cas# prechar g e time 10 ns t31 cas# active to ras# [ 1-0 ] active dela y 25 ns t32 cas# inactive to ras# [ 1-0 ] inactive dela y 25 ns t33 ras# active to ras# active dela y ( durin g refresh ) 55 ns t34 ras# inactive to ras# active dela y ( durin g refresh ) 55 ns 6.5.3 at bus timing t46 atclk fallin g ed g e to bale active dela y 530ns t47 atclk risin g ed g e to bale inactive dela y 530ns t48 atclk fallin g ed g e to cmd active dela y 530ns t49 atclk risin g ed g e to cmd active dela y 530ns t50 atclk risin g ed g e to cmd inactive dela y 530ns t51 m16# to atclk risin g ed g e setup time 8 ns t52 m16# from atclk risin g ed g e hold time 8 ns t53 io16# to atclk risin g ed g e setup time 10 ns t54 io16# from atclk risin g ed g e hold time 10 ns t55 chrdy to atclk risin g ed g e setup time 12 ns t56 chrdy from atclk risin g ed g e hold time 12 ns t57 fbclk fallin g ed g e to hold active dela y 516ns t58 fbclk risin g ed g e to hold inactive dela y 516ns t59 atclk risin g ed g e to refresh# active dela y 830ns t60 atclk risin g ed g e to refresh# inactive dela y 830ns t70 0ws# to atclk fallin g ed g e setup time t71 0ws# from atclk fallin g ed g e hold time t85 a [ 9:0 ] valid to kbdcs# active dela y 30 ns t86 a [ 9:0 ] invalid to kbdcs# inactive dela y 30 ns t106 cd [ 31:0 ] valid to sd [ 15:0 ] valid dela y 917ns t107 cd [ 31:0 ] valid to mp [ 3:0 ] valid dela y 818ns t108 cd [ 31:0 ] invalid to sd [ 15:0 ] invalid dela y 818ns sym. parameter min typ max unit 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 181 revision: 3.0 t109 cd [ 31:0 ] invalid to mp [ 3:0 ] invalid dela y 818ns t110 sd [ 15:0 ] valid to cd [ 31:0 ] valid dela y 816ns t111 sd [ 15:0 ] valid to mp [ 3:0 ] valid dela y 12 20 ns t112 sd [ 15:0 ] invalid to cd [ 31:0 ] invalid dela y 816ns t113 sd [ 15:0 ] invalid to mp [ 3:0 ] dela y 12 20 ns t114 sd [ 15:8 ] valid to sd [ 7:0 ] dela y 816ns t115 sd [ 15:8 ] invalid to sd [ 7:0 ] dela y 918ns t116 chck# active to nmi dela y 18 ns t131 atclk ed g e to sdenl# dela y 1/2 atclk t132 atclk ed g e to sdenh# dela y 1/2 atclk t133 fbclk risin g ed g e to romcs# active dela y 30 ns t134 atclk fallin g ed g e to xdir active dela y 5 20 ns t136 atclk risin g ed g e to xdir inactive dela y 520ns t137 atclk risin g ed g e to i/o cmd# inactive dela y 520ns t138 atclk fallin g ed g e to i/o cmd# active dela y 520ns t171 cpuclk risin g ed g e to sdenh# inactive dela y 5ns t172 cpuclk risin g ed g e to sdenl# inactive dela y 5ns t173 cpuclk risin g ed g e to sdir inactive dela y 5ns t174 at bus turn-around time 1/2 atclk ns t175 next atclk ed g e to sdenh# active dela y 20 ns t176 next atclk ed g e to sdenl# active dela y 20 ns t177 next atclk ed g e to sdir active dela y 20 ns 6.5.4 reset and local bus timing t102 fbclk/cpuclk risin g ed g e to cpurst/sreset active dela y 81015ns t105 fbclk/cpuclk risin g ed g e to cpurst/sreset inactive dela y 81015ns t117 ads# setup time 8 ns t170 ads# hold time 5 ns t118 ldev# setup time 8 ns t119 ldev# hold time 5 ns t121 rdy# active to cpuclk risin g ed g e dela y 8ns t122 rdy# inactive from cpuclk risin g ed g e dela y 5ns t165 cpu reset time 190 cpuclk sym. parameter min typ max unit 82C465MV/mva/mvb opti ? pa g e 182 912-3000-016 revision: 3.0 a. ma bus timin g dela y s depend heavil y on bus loadin g . timin g t24 assumes 12 dram devices on the bus. add approximatel y a 7ns dela y for each additional bank of 12 devices. if heav y -dut y ma bus drive is enabled ( syscfg a1h [ 4 ] = 1 ), add a 5ns dela y for each additional bank. 6.5.5 power management timing t140 atclk risin g ed g e to pio active dela y 40 ns t141 atclk risin g ed g e to ma bus valid dela y 25 ns t142 atclk risin g ed g e to ma bus invalid dela y 20 ns t143 atclk risin g ed g e to ppwrl active dela y 25 ns t144 atclk risin g ed g e to ppwrl inactive dela y 25 ns t146 stop clock dela y setup in syscfg b0h t150 stop clock dela y setup in syscfg b0h t151 7/8 resume recover y time t152 1/8 resume recover y time t158 ppwrl width ( atclk not runnin g) 1/2 ( 15us ) sqwin clk t169 ppwrl width ( atclk runnin g) 1atclk t180 rdy# inactive to hold active dela y 1atclk sym. parameter min typ max unit 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 183 revision: 3.0 6.6 timing diagrams figure 6-1 rom cycle with sdenh#, sdenl# (l2 cache enabled) t46 t47 t134 t136 t49 t132 t131 t133 1fffff0 ea 5b e0 00 0123 valid fbclk atclk ads# a [ 24:0 ] sa [ 1:0 ] sd [ 15:0 ] cd [ 31:0 ] be [ 3:0 ] # rdy# bale xdir mrd# sdenh# sdenl# sdir romcs# 82C465MV/mva/mvb opti ? pa g e 184 912-3000-016 revision: 3.0 figure 6-2 isa bus cycle t46 t47 t48 t71 t70 t55 t56 t49 t133 t134 t51 t52 t53 t54 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 one more atclk dela y if at extra ws is set 8-bit isa bus c y cles bale will be g enerated 1 atclk late if fast at c y cle option is disabled 16-bit isa bus c y cles one more atclk dela y if at extra ws is set one more atclk dela y if at extra ws is set fbclk atclk ads# m/io# , d/c# , w/r# , a [ 31:2 ] bale 8-bit isa bus cmd#s mcs16# iocs16# 0ws# chrdy rdy# 16-bit memr#/memw# 16-bit ior#/iow# mcs16# iocs16# rdy# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 185 revision: 3.0 figure 6-3 keyboard controller access cycle figure 6-4 cd[31:0] to sd[15:0] and mp[3:0] valid and invalid delay figure 6-5 sd[15:0] to cd[31:0] and mp[3:0] valid and invalid delay t46 t47 t134 t136 t85 t86 t48 t50 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t fbclk atclk ads# m/io# , d/c# , w/r# , a [ 31:2 ] sa [ 9:2 ] bale xdir kbdcs# ior#/iow# rdy# t106 t108 t107 t109 cd [ 31:0 ] sd [ 15:0 ] mp [ 3:0 ] t110 t112 t111 t113 sd [ 15:0 ] cd [ 31:0 ] mp [ 3:0 ] 82C465MV/mva/mvb opti ? pa g e 186 912-3000-016 revision: 3.0 figure 6-6 data valid and invalid delay between sd[15:8] and sd[7:0] data swapping figure 6-7 nmi valid delay related to iochk# figure 6-8 l2 cache read miss - dirty, double bank cache t114 t115 sd [ 15:8 ] sd [ 7:0 ] t116 nmi chck# t16 t17 t12 t13 t1 t2 t3 t10 t11 t14 t15 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 fbh valid ta g cpuclk ads# eca3 eca2 brdy# ecawe# ocawe# beoe# booe# dwe# rasx# cas [ 3:0 ] # rdy# drty tagwe# tag [ 7:0 ] 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 187 revision: 3.0 figure 6-9 l2 cache write 0 wait state, not dirty figure 6-10 l2 cache write, dirty t9a t9b t7 t9 t12 t13 t1 t2 t2 t1 clk ads# blast# m/io# , d/c# , w/r# , a [ 31:2 ] ecawe#/ocawe# ecawe#/ocawe# drty tagwe# brdy# t8 t7 t9 t12 t13 t12 t13 0 wait state dirt y 1 wait state dirt y t1 t2 t1 t2 t2 clk ads# blast# m/io# , d/c# , w/r# , a [ 31:2 ] ecawe#/ocawe# drty tagwe# brdy# 82C465MV/mva/mvb opti ? pa g e 188 912-3000-016 revision: 3.0 figure 6-11 l2 cache burst read 3-2-2-2 for double bank t1 t2 t3 t16 t17 t4 t5 t1 t2 t2 t2 t1 t2 t2 t2 t2 t2 clk ads# m/io# , d/c# , w/r# , a [ 31:2 ] beoe# booe# eca3 eca2 brdy# ecawe#/ocawe# tagwe# drty rdy# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 189 revision: 3.0 figure 6-12 l2 cache burst read 3-2-2-2 for single bank t1 t3 t16 t17 t4 t5 t1 t2 t2 t2 t1 t2 t2 t2 t2 t2 clk ads# m/io# , d/c# , w/r# , a [ 31:2 ] beoe# booe# eca3 eca2 brdy# ecawe#/ocawe# tagwe# rdy# 82C465MV/mva/mvb opti ? pa g e 190 912-3000-016 revision: 3.0 figure 6-13 l2 cache burst read 2-1-1-1 cycle for double bank t1 t3 t1 t2 t16 t17 t16 t4 t5 t4 t1 t2 t2 t2 t1 t2 clk ads# m/io# , d/c# , w/r# , a [ 31:2 ] beoe# booe# eca3 eca2 brdy# ecawe#/ocawe# tagwe# drty rdy# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 191 revision: 3.0 figure 6-14 hitm# active with l2 cache hit, l2 cache 3-2-2-2 write cycle (cache 0 wait write) note: samplin g of hitm# is pro g rammable to be in either second or third clock after eads#. t167 t168 t161 t161 t7 t8 fbclk eads# iochrdy hitm# hold hlda ads# brdy# ecawe# ocawe# 82C465MV/mva/mvb opti ? pa g e 192 912-3000-016 revision: 3.0 figure 6-15 hitm# signal active, burst write back cycle, 1 wait state dram write setup note: samplin g of hitm# is pro g rammable to be in either second or third clock after eads#. t161 t161 t162 fbclk eads# ahold iochrdy hitm# hold hlda ads# brdy# ras# cas# dwe# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 193 revision: 3.0 figure 6-16 refresh cycle figure 6-17 dram burst read 5-4-4-4 (page hit) t31 t32 t33 t34 t57 t58 t59 t60 ti ti ti ti ti ti ti ti ti ti ti ti ti ti ti ti ti ti ti fbclk atclk cas [ 3:0 ] # ras0# ras1# ras2# ras3# hold hlda refresh# t30 t18 t19 t24 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t2 t2 clk ads# a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# rdy# 82C465MV/mva/mvb opti ? pa g e 194 912-3000-016 revision: 3.0 figure 6-18 dram burst read x-2-2-2 (page miss) figure 6-19 dram burst read 3-2-2-2 (page hit) t29 t29 t30 t30 t22 t23 t20 t21 t25 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t1 clk ads# mio , dc , wr , a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# rdy# t30 t30 t20 t21 t24 t1 t2 t2 t2 t2 t2 t2 t2 t2 t1 clki ads# mio , dc , wr , a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# rdy# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 195 revision: 3.0 figure 6-20 dram burst read 4-3-3-3 (page hit) figure 6-21 dram burst read x-3-3-3, 1 wait page miss t30 t18 t19 t24 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 cpuclk ads# a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# t30 t18 t19 t24 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 cpuclk ads# a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# 82C465MV/mva/mvb opti ? pa g e 196 912-3000-016 revision: 3.0 figure 6-22 dram burst read x-3-3-3, 0 wait page miss figure 6-23 dram write wait state (without l2 cache support) t30 t18 t19 t24 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 cpuclk ads# a [ 31:2 ] ras0# cas [ 3:0 ] # ma [ 11:0 ] dwe# blast# brdy# t18 t19 t18 t19 t26 t27 t26 t27 t1 t2 t2 t1 t2 t2 t2 0 wait state write* 1 wait state write** fbclk ads# brdy# cas# ras# dwe# * 0 wait state c y cle takes three clocks to be completed. ** 1 wait state c y cle takes four clocks to be completed. 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 197 revision: 3.0 figure 6-24 single local bus cycle figure 6-25 reset timing t119 t117 t170 t118 t121 t122 oscclk2 fbclk cpuclk ads# addr ldev# rdy# t105 t165 t103 t104 t102 fbclk cpuclk cpurst/sreset rdy# 82C465MV/mva/mvb opti ? pa g e 198 912-3000-016 revision: 3.0 figure 6-26 low word isa bus memory read to high word local bus with sdenl#, sdenh#, and sdir active figure 6-27 write ppwr[3:0] with '1111' buffer driven t174 465 driven t175 t132 t171 t176 t131 t172 t177 t173 zzzz valid data 'ea' ea ea cpuclk atclk rdy# sdenh# sdenl# sdir mrd# cd [ 31:16 ] sd [ 15:0 ] t169 t143 t144 t141 t142 0000024 00ff 4ff fbclk atclk ads# rdy# a [ 24:0 ] sd [ 15:0 ] bale iow# ppwrl ma 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 199 revision: 3.0 figure 6-28 pio timing example (pio2) t140 0000022 0056 zzzz 0044 0000024 fbclk atclk ads# rdy# a [ 24:0 ] sd [ 15:0 ] bale iow# pio2 82C465MV/mva/mvb opti ? pa g e 200 912-3000-016 revision: 3.0 figure 6-29 suspend sequence after writing '1' to syscfg 50h[0] notes: the timin g in this waveform is not proportional. the dia g ram is used to show the se q uence of events 1 throu g h 8 onl y . 1. 82C465MV asserts stpclk# si g nal to cpu. 2. cpu responds with stop g rant c y cle. 3. one atclk after the rdy# si g nal is asserted , 82C465MV asserts hold to cpu. 4. cpu responds with hlda. 5. 82C465MV asserts tris# and drives its output pins accordin g to suspend state. 6. 82C465MV asserts suspend refresh within 1 1/2 32khz clock ( ~45us ) . normal refresh is still enabled within this period ( not shown in the dia g ram ) . 7. 82C465MV stops the followin g clocks in low state: cpuclk , fbclk , atclk , kbclk , kbclk2 8. one 32khz clock after suspend refresh , 82C465MV to gg les ppwr0-1 to turn off clock g enerator. t180 t158 t158 1 2 3 4 5 6 7 0000010 fbclk stpclk# ads# rdy# a [ 24:0 ] hlda hold ppwrl tris# sqwin ras# cas# 8 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 201 revision: 3.0 figure 6-30 resume sequence notes: the timin g in this waveform is not proportional. the dia g ram is used to show the se q uence of events 1 throu g h 10 onl y . 1. resume source sets pmi#6 active. ( no smi g enerated if alread y in smm. ) 2. ppwr0-1 to gg le to enable clock g enerator. ppwr10 also set to low for resume reset. rst4# asserted for resume reset ( also epmi2 , if enabled ) . 3. after 7/8 of resume recover y time , 82C465MV resumes cpuclk , fbclk , atclk. 4. resume recover y time expires. 5. 1/2 32khz clock later , 82C465MV to gg les ppwr10 to end resume reset. 6. suspend refresh ended , normal refresh started. 7. 82C465MV de-asserts tris# and drives its output pins back to normal state , and rst4#/epmi2 de-asserted to end the resume reset. 8. 82C465MV de-asserts stpclk# to the cpu. 9. 82C465MV de-asserts the hold si g nal. 10. cpu de-asserts the hlda si g nal. t151 t152 t158 t158 1 2 2 2 3 4 5 6 7 7 8 9 10 fbclk sqwin pmi#6 ppwrl rst4# tris# ras# cas# stpclk# hold hlda resu/recov 82C465MV/mva/mvb opti ? pa g e 202 912-3000-016 revision: 3.0 figure 6-31 timer time-out and smi generation sequence notes: the timin g in this waveform is not proportional. the dia g ram is used to show the se q uence of events 1 throu g h 4 onl y . idle timer count is not visible. it is shown here for illustrative purposes onl y . other timers also behave in this manner. 1. idle timer times out. 2. 82C465MV activates smi# si g nal to cpu. 3. cpu returns smiact#. 4. 82C465MV de-asserts smi# after smiact# g oes active. 3210 1 2 3 4 fbclk timer clk derived from 32khz idle timer count pmi#4 smi# smiact# 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 203 revision: 3.0 figure 6-32 apm stop clock sequence notes: the timin g in this waveform is not proportional. the dia g ram is used to show the se q uence of events 1 throu g h 10 onl y . 1. write syscfg 50h [ 3 ] = 1 to enable 82C465MV to start stop clock c y cle. 2. 82C465MV drives stpclk# low. 3. cpu stop g rant c y cle. 4. 82C465MV asserts hold. 5. cpu responds with hlda. 6. 82C465MV stops cpuclk or chan g es the clock accordin g to syscfg 41h [ 4:2 ] . 7. irq wakes up 82C465MV from stop clock and tri gg ers resume speed se q uence. 8. both fbclk and cpuclk resume back to full speed. 9. after stpclk# is de-asserted , 82C465MV releases hold. 10. cpu releases hlda. t150 00000024 0000010 1 2 3 4 5 6 7 8 9 10 cpuclk a [ 24:0 ] ads# read y # iow# hold hlda stpclk# irq 82C465MV/mva/mvb opti ? pa g e 204 912-3000-016 revision: 3.0 figure 6-33 doze sequence notes: the timin g in this waveform is not proportional. the dia g ram is used to show the se q uence of events 1 throu g h 11 onl y . 1. doze_timer times out. 2. 82C465MV asserts stpclk# si g nal. 3. cpu responds with stop g rant c y cle. 4. 82C465MV chan g es the fbclk , cpuclk accordin g to syscfg 41h [ 4:2 ] . 5. stop clock dela y accordin g to syscfg b0h. 6. irq line g oes active to tri gg er the s y stem back to normal speed. 7. doze_timer reload. 8. 82C465MV asserts stop clock si g nal. 9. cpu responds with stop g rant c y cle. 10. 82C465MV chan g es the clocks back to normal speed. 11. 82C465MV holds the stpclk# si g nal active for the time selected in syscfg b0h. * r = reload value t146 0000010 02 01 00 r* r-1 r-2 r- 6 5 8 7 3 1 2 9 10 11 cpuclk a [ 24:0 ] ads# rdy# doze_timer timer clk derived from 32khz stpclk# irq 4 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 205 revision: 3.0 6.7 functional memory timing diagrams 6.7.1 fast page mode (fpm) dram figure 6-34 fpm dram, 3-2-2-2 page hit read 82C465MV/mva/mvb opti ? pa g e 206 912-3000-016 revision: 3.0 figure 6-35 fpm dram, 5-2-2-2 inactive page miss read figure 6-36 fpm dram, 8-2-2-2 active page miss read 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 207 revision: 3.0 figure 6-37 fpm dram, 4-3-3-3 page hit read figure 6-38 fpm dram, 8-3-3-3 inactive page miss read 82C465MV/mva/mvb opti ? pa g e 208 912-3000-016 revision: 3.0 figure 6-39 fpm dram, 11-3-3-3 active page miss read figure 6-40 fpm dram, 4-3-3-3 page hit read (0 wait state page miss) 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 209 revision: 3.0 figure 6-41 fpm dram, 6-3-3-3 inactive page miss read (0 wait state page miss) figure 6-42 fpm dram, 9-3-3-3 active page miss read (0 wait state page miss) 82C465MV/mva/mvb opti ? pa g e 210 912-3000-016 revision: 3.0 figure 6-43 fpm dram, 5-4-4-4 page hit read figure 6-44 fpm dram, 8-4-4-4 inactive page miss read 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 211 revision: 3.0 figure 6-45 fpm dram, 12-4-4-4 active page miss read figure 6-46 fpm dram, 0 wait state write 82C465MV/mva/mvb opti ? pa g e 212 912-3000-016 revision: 3.0 figure 6-47 fpm dram, 1 wait state write figure 6-48 fpm dram, 5-2-2-2 inactive page miss with ras 1/2 clk early 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 213 revision: 3.0 6.7.2 extended data out (edo) figure 6-49 edo, 3-1-1-1 page hit read 82C465MV/mva/mvb opti ? pa g e 214 912-3000-016 revision: 3.0 figure 6-50 edo, 5-1-1-1 inactive page miss with ras 1/2 clk early figure 6-51 edo, 8-1-1-1 active page miss with ras 1/2 clk early 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 215 revision: 3.0 figure 6-52 edo, 10-1-1-1 active page miss with normal ras figure 6-53 edo, 3-2-2-2 page hit read 82C465MV/mva/mvb opti ? pa g e 216 912-3000-016 revision: 3.0 figure 6-54 edo, 6-2-2-2 inactive page miss figure 6-55 edo, 10-2-2-2 active page miss read 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 217 revision: 3.0 figure 6-56 edo, 4-2-2-2 page hit read figure 6-57 edo, 7-2-2-2 inactive page miss 82C465MV/mva/mvb opti ? pa g e 218 912-3000-016 revision: 3.0 figure 6-58 edo, 11-2-2-2 active page miss 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 219 revision: 3.0 7.0 test mode information the 82C465MV part can be forced to tristate all of its outputs at an y time for board level testin g . once this mode has been commanded , all chip operatin g and status information becomes invalid. therefore , the chip must be powered down and then restarted after this feature is used. to enter test mode: ? set pins 85 , 86 , and 139 low. ? set pins 45 , 87 , 128 , and 140 hi g h. test mode is enabled b y a decode of combinatorial lo g ic. therefore , the order in which these pins are brou g ht hi g h or low is unimportant. to clear test mode , power down the s y stem and clear the hi g h/low settin g s used to enable test mode. 82C465MV/mva/mvb opti ? pa g e 220 912-3000-016 revision: 3.0 82C465MV/mva/mvb opti ? 912-3000-016 pa g e 221 revision: 3.0 8.0 mechanical package outline figure 8-1 208-pin plastic quad flat pack (qfp) 82C465MV/mva/mvb opti ? pa g e 222 912-3000-016 revision: 3.0 appendix a 912-3000-016 page 223 revision: 3.0 opti ? a. incompatibilities with the 82c463mv the 82C465MV is intended to be as full y compatible as pos- sible with the 82c463mv. however, certain architectural and pro g rammin g features should be noted. a.1 power plane changes the pins with alternative functions dackmux0-2 and dack2# are 3.3v outputs on the 82C465MV; these were 5.0v outputs on the 82c463mv. some existin g 82c463mv desi g ns could exhibit a sli g ht increase in power consumption dependin g on the lo g ic famil y used to interface to these si g - nals. if the 82C465MV is used in a new desi g n, these si g nals are relocated to a 5.0v plane and do not affect current draw. a.2 read cycle efficiency on slower s y stems, the 82c463mv memor y controller could be pro g rammed to a 2-1-1-1 or 3-1-1-1 c y cle due to the fact that the chipset used a 2x input clock. the 82C465MV uses onl y a 1x input clock to run its memor y controller. therefore, the fastest memor y c y cle possible on the 82C465MV is 3-2-2- 2. in most practical applications, the speed difference is not detectable because most operation occurs from the cpu cache. since burst read c y cles are onl y used to refill the cache and this process takes place concurrentl y with internal processin g , there is no substantial performance loss. however, a perceived performance reduction can occur if an 82c463mv-compatible bios is used. the dram c y cle con- troller bits chan g ed meanin g between the 82c463mv and the 82C465MV and settin g s that used to allow 3-1-1-1 and 3-2-2- 2 operation now select 4-3-3-3 operation. syscfg 35h should be modified as soon as possible after boot, either throu g h a bios modification or a simple executable file. a.3 ads# sampling on ver y fast s y stems, predictive samplin g of ads# to deter- mine c y cle t y pe for better efficienc y is not alwa y s effective. the safest wa y to determine c y cle t y pe is to latch the m/io#, w/r#, and d/c# status on the risin g ed g e of ads#. the 82c463mv could not run above 33mhz, so this samplin g was never an issue. but since the 82C465MV can run as hi g h as 50mhz, it must default to the safe mode for latchin g sta- tus. a si g nificant performance improvement can be made to slower s y stems, therefore, if the 82c463mv-compatible mode of samplin g is enabled throu g h settin g syscfg d1h[6] = 1. a.4 removal of sequencer the 82c463mv contained a se q uencer that could perform limited power mana g ement functions on its own without cpu intervention. because the vast ma j orit y of cpus now avail- able provide smi control, the se q uencer feature has been removed. a.5 default refresh rate change since the se q uencer has been removed, the g lobal se q uencer enable bit, syscfg 67h[5], has been redefined to form part of the refresh rate selection bits. most 82c463mv- based bios enabled this bit. with this settin g , the default refresh rate on the 82C465MV ( both active mode and sus- pend mode ) will be ever y 31 s instead of the recommended 15 s. while most modern dram can handle slower refresh rates, the bios should be modified for the correct rate if nec- essar y . a.6 i/o blocking default change syscfg dbh[7] defaults to 0 and disables i/o blockin g on next access. it should be set to 1 to be compatible with 82c463mv software. the 82c463mv part had no bit to con- trol this feature, which was alwa y s set to block. a.7 suspend mode dackmux parking syscfg d5h[7:6] default to a state that parks the dack- mux lines differentl y than the 82c463mv part, such that dack2# sits low instead of dack4#. these bits should be reset if needed ( if dack2# low will cause problems ) . appendix a page 224 912-3000-016 revision: 3.0 opti ? appendix b 912-3000-016 page 225 revision: 3.0 opti ? b. compact isa specification this document describes a new opti interface that will be used to interface the 82c852 pcmcia controller to opti s y stem controller chipsets. this interface ma y also be used to interface opti peripheral products in the future. the interface is opti-proprietar y , and ma y be licensed to others in the future. b.1 compact isa overview the compact isa interface coexists with the standard isa interface. chips that support the compact isa interface en j o y a reduced isa pin count because address si g nals and com- mand information are strobed in on the sd[15:0] bus. isa pins eliminated are: ? sa[23:0] ( 24 pins ) ? iord#, iowr#, mrd#, mwr#, smrd#, smwr#, sbhe#, nows#, aen, io16#, m16# ( 11 pins ) ? irq3, 4, 5, 6, 7, 10, 11, 12, 14, 15; drq/dack#0, 1, 2, 3, 5, 6, 7, and tc ( 25 pins ) compact isa defines onl y two new si g nals, cmd# and sel#/ atb#, for a total re q uirement of 22 pins. the pin count reduc- tion over standard isa is 58 pins. compact isa performance is comparable with that of 16-bit isa bus peripheral devices. moreover, compact isa does not interfere with standard isa operations. the complete si g nal set of compact isa, referred to in the descriptions as cisa, is shown below. table b-1 compact isa (cisa) interface signals *peripheral side name type* description mad[15:0] i/o multiplexed bus: used to transfer address, command, data, irq, drq, dack information. atclk i standard isa clock: cisa device uses risin g ed g e to clock in the first ( address ) phase. ale i standard isa address latch enable: cisa peripheral device uses risin g ed g e of ale to latch the second ( address and command ) phase. cisa host uses fallin g ed g e of ale to latch cmd# from peripheral device. cmd# i command indication: common to host and all devices on the cisa bus. the cisa host asserts cmd# durin g the data phase of the c y cle to time the standard isa command ( iord#/wr#, mrd#/wr# ) , and also asserts cmd# to acknowled g e sel#atb#. sel#/atb# ( also clkrun# ) o tristate device selected / isa bus backoff request: common to all peripheral devices on the cisa bus. when ale is hi g h, the cisa device asserts sel# to indicate to the host that it is claimin g the c y cle. when ale is low, the cisa device drives this si g nal to indicate that it has an interrupt and/or dma re q uest to make; the host acknowled g es b y assertin g cmd#. after the host has preset the cisa device in a stop clock mode, the device can assert this si g nal as y nchronousl y to restart the clock. iochrdy o tristate standard isa cycle extension request: used durin g memor y and i/o c y cles. rstdrv i standard isa bus reset appendix b page 226 912-3000-016 revision: 3.0 opti ? b.2 compact isa cycle definition the mad[15:0] lines contain different information for each phase of the bus c y cle. the use of these lines varies accord- in g to whether a memor y c y cle or an i/o c y cle is bein g run. certain c y cle definition bits are common to all c y cles, as shown in table b-2. retained values entries marked "same" retain the same value as in the previ- ous phase, in order to reduce transitions where possible. however, the cisa peripheral device decode lo g ic must not assume that these values will be stable. the bits ma y be reassi g ned in the future. b.2.1 memory cycle the mad[15:0] bit meanin g s for each phase of a memor y c y cle are shown in table b-3. the m/io# bit is alwa y s 1 for memor y c y cles. the g eneral structure of compact isa memor y c y cles is shown in fi g ure b-1 and fi g ure b-2. table b-2 common mad bit usage signal phase 1 phase 2 mad0 m/io# indication bit; used to determine the c y cle t y pe. w/r# indication bit mad1 i/d# indication bit. it is alwa y s 0 if m/io# = 1, and selects between i/o and dma c y cles if m/io# = 0. sbhe# indication bit mad2 usa g e varies. isa# timin g indication bit; described in the "perfor- mance control" section of this document. table b-3 mad bits during memory cycles phase mad15 mad14 mad13 mad12 mad11 mad10 mad9 mad8 mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 1 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 i/d# = 0 m/io# = 1 2 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 same same same isa# sbhe# w/r# 3 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 appendix b 912-3000-016 page 227 revision: 3.0 opti ? figure b-1 compact isa memory cycle operation, fast cisa timing* *c y cle optionall y extended b y iochrdy shown in g ra y . 1. cisa host g ets address from the cpu address lines and b y te enable lines. the host then drives out a[23:10] + m/ io# on mad[15:0] with m/io# hi g h ( memor y) . 2. cisa peripheral device latches address and m/io# on the risin g ed g e of atclk and decodes the information. 3. host drives out remainin g address + command on mad[15:0]. 4. host asserts ale. if c y cle belon g s to cisa peripheral device, it asserts sel# and latches the address and command from mad[15:0] on the risin g ed g e of ale. device latches isa# = 1 at this time. 5. host and other cisa devices reco g nize the sel# func- tion of sel#/atb# b y seein g ale hi g h when samplin g sel#/atb# low on the risin g ed g e of atclk. host de- asserts ale and stops drivin g address on this risin g atclk ed g e. 6. for reads, the host tristates the mad[15:0] buffers. for writes, it drives the write data onto mad[15:0]. host asserts cmd# s y nchronous to the risin g ed g e of atclk and can optionall y inhibit its mrd#/mwr# lines. 7. c y cle is 0 wait states as indicated b y isa# = 1. cisa peripheral device can brin g iochrdy low as y nchro- nousl y after cdm# g oes active to extend the c y cle. 8. device brin g s iochrdy hi g h s y nchronous to the fallin g ed g e of atclk to allow c y cle completion. 9. host de-asserts cmd# on the same risin g ed g e where it samples iochrdy hi g h. ale atclk cmd# mad[15:0] (sd[15:0]) 2 3 4 driven by host iochrdy 5 address phase 1 d[15:0] address phase 2 1 ca[25:0] 6 sel#/atb# driven by device 7 8 9 appendix b page 228 912-3000-016 revision: 3.0 opti ? figure b-2 compact isa memory cycle operation, standard isa timing* *c y cle optionall y extended b y iochrdy shown in g ra y . 1. cisa host g ets address from the cpu address lines and b y te enable lines. the host then drives out a]23:10] + m/ io# on mad[15:0] with m/io# hi g h ( memor y) . 2. cisa peripheral device latches address and m/io# on the risin g ed g e of atclk and decodes the information. 3. host drives out remainin g address + command on mad[15:0]. 4. host asserts ale. if c y cle belon g s to cisa peripheral device, it asserts sel# and latches the address and command from mad[15:0] on the risin g ed g e of ale. device latches isa# = 0 at this time. 5. host and other cisa devices reco g nize the sel# func- tion of sel#/atb# b y seein g ale hi g h when samplin g sel#/atb# low on the risin g ed g e of atclk. host de- asserts ale and stops drivin g address on this risin g atclk ed g e. 6. for reads, the host tristates the mad[15:0] buffers. for writes, it drives the write data onto mad[15:0]. host asserts cmd# s y nchronous to the risin g ed g e of atclk and can optionall y inhibit its mrd#/mwr# lines. 7. c y cle is not zero wait states, as indicated b y isa# = 0. cisa peripheral device can brin g iochrdy low as y n- chronousl y after cdm# g oes active to extend the c y cle further. 8. device brin g s iochrdy hi g h as y nchronousl y to allow c y cle completion. 9. host de-asserts cmd# on the next risin g ed g e of atclk after the risin g ed g e atclk ed g e on which it samples iochrdy hi g h. ale atclk cmd# mad[15:0] (sd[15:0]) 2 3 4 driven by host iochrdy 5 address phase 1 d[15:0] address phase 2 1 ca[25:0] 6 sel#/atb# driven by device 7 8 9 appendix b 912-3000-016 page 229 revision: 3.0 opti ? b.2.2 i/o cycle the mad[15:0] bit meanin g s for each phase of an i/o c y cle are shown below. the m/io# bit is alwa y s 0, and the i/d# bit is alwa y s 1, for an i/o c y cle. the g eneral structure of compact isa i/o c y cles is shown in fi g ure b-3. figure b-3 compact isa i/o cycle operation* *c y cle optionall y extended b y iochrdy shown in g ra y . 1. cisa host g ets address from the cpu address lines and b y te enable lines. the host then drives out a[15:2] + i/d# = 1 + m/io# = 0 ( i/o c y cle ) . 2. cisa peripheral device latches address and m/io# on the risin g ed g e of atclk and decodes the information. 3. host drives out remainin g address + command on mad[15:0]. 4. host asserts ale. if c y cle belon g s to cisa peripheral device, it asserts sel# and latches the address and command from mad[15:0] on the risin g ed g e of ale. 5. host and other cisa devices reco g nize the sel# func- tion of sel#/atb# b y seein g ale hi g h when samplin g sel#/atb# low on the risin g ed g e of atclk. host de- asserts ale and stops drivin g address on this risin g atclk ed g e. 6. for reads, the host tristates the mad[15:0] buffers. for writes, it drives the write data onto mad[15:0]. 7. host asserts cmd# s y nchronous to the fallin g ed g e of atclk to run the command and can optionall y inhibit its ior#/iow# lines. 8. c y cle is never zero wait state. cisa peripheral device can brin g iochrdy low as y nchronousl y after cdm# g oes active, usin g standard isa setup timin g , to extend the c y cle further. note that if cisa peripheral device pro- vides a brid g e to another device ( a pcmcia slot, for example ) , the device on the secondar y bus must be able to return iochrdy soon enou g h to meet setup timin g on the cisa interface. 9. device brin g s iochrdy hi g h as y nchronousl y to allow c y cle completion. table b-4 mad bits during i/o cycles phase mad15 mad14 mad13 mad12 mad11 mad10 mad9 mad8 mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 1 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa15 sa14 sa13 sa12 sa11 sa10 i/d# = 1 m/io# = 0 2 same same same same same same same same sa1 sa0 same same same isa# = 0 sbhe# w/r# 3 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 ale atclk cmd# mad[15:0] (sd[15:0]) 2 3 4 driven by host iochrdy 5 address phase 1 d[15:0] address phase 2 1 ca[25:0] 6 sel#/atb# driven by device 7 8 9 10 appendix b page 230 912-3000-016 revision: 3.0 opti ? 10. host de-asserts cmd# on the next fallin g ed g e of atclk after the risin g ed g e atclk ed g e on which it samples iochrdy hi g h. b.2.3 dma on the cisa/isa bus dma operations are handled ver y specificall y for cisa peripheral devices. both cisa memor y devices and cisa dma devices can be involved in a dma transfer, possibl y at the same time. the cisa host must handle each situation. the central consideration is that the cisa host must be able to distin g uish between the dma channels that are on the isa bus and those that are on the cisa bus. this is a simple mat- ter when the host also incorporates the dma controller: because the host is responsible for latchin g the drq drive- back information, it can determine on a c y cle-b y -c y cle basis whether the dma device bein g serviced is on cisa or on isa accordin g to whether it latched drq active for that channel from a cisa driveback c y cle. because the host has this knowled g e, the cisa dma device does not need to assert sel# on a dack# c y cle. the host alread y knows the c y cle belon g s to a cisa dma device and does not need to see sel# for the i/o portion of the c y cle. this inhibition of sel# is most important when a cisa mem- or y device is respondin g to the memor y portion of the c y cle: the cisa memor y device must respond as alwa y s with sel#, and there would be contention ( on deassertion ) if the cisa dma device asserted sel# as well. the host must foresee the followin g two situations. ? dma transfer between isa dma device and any mem- ory device (system dram, isa memory, or cisa mem- ory) - the host runs a standard cisa memor y c y cle ( i/d# = 0, m/io# = 1 ) alon g with the isa memor y -i/o c y cle. if the selected memor y is present on cisa, the device will respond to the access with sel# as usual. the host must drop ale if sel# is returned. ? dma transfer between cisa dma device and memory - the host runs a cisa dack# c y cle ( i/d# = 0, m/io# = 0 ) . if a cisa memor y device claims this c y cle it responds with sel# as usual. the memor y device can drive iochrdy low to extend the c y cle if desired. the cisa dack# c y cle is described below. b.2.4 dack# cycle the dack# c y cle is uni q ue in that it has properties of a mem- or y c y cle but is directed to an i/o device. basicall y , the dack# c y cle is a memor y c y cle whose address must be decoded b y an y cisa memor y device on the bus. sbhe# and w/r# reference the memor y device, not the i/o device; the i/o device must assume the opposite sense of w/r# for its portion of the c y cle. onl y the memor y device responds with sel#; the dma ( i/o ) device never responds. the cmd# timin g will be the wider pulse of memw#/ior# or memr#/ iow#. the mad[15:0] bit meanin g s for each phase of a dma acknowled g e c y cle are shown in table b-5. the m/io# bit is alwa y s 0, and the i/d# bit is alwa y s 0, for a dack# c y cle. dmx2-0 encode the number of the dack#. for example, dmx2-0 = 010 indicate dack2# active. tc is hi g h if the dack# is bein g returned with the terminal count indication. note that there is no isa# bit, since there is no fast c y cle pos- sible. the g eneral structure of compact isa dack# c y cles is shown in fi g ure b-4. table b-5 mad bits during dma acknowledge cycles phase mad15 mad14 mad13 mad12 mad11 mad10 mad9 mad8 mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 1 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 i/d# = 0 m/io# = 0 2 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 dmx2 dmx1 dmx0 tc sbhe# w/r# 3 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 appendix b 912-3000-016 page 231 revision: 3.0 opti ? figure b-4 compact isa dack# cycle operation 1. cisa host g ets address form the cpu address lines and b y te enable lines. the host then drives out a[23:0] + i/d# = 0 + m/io# = 0 ( dack# c y cle ) . 2. cisa dam device, and possibl y cisa memor y device, latches address and c y cle t y pe information on the risin g ed g e of taclk and decodes the information. 3. host drives out remainin g command information on mad[15:0]. 4. host asserts ale. cida dma device does not assert sel# but latches the address and command from mad[15:0] on the risin g ed g e of ale. an y cisa memor y device present latches address and command, decodes them, and asserts sel# if appropriate. 5. host de-asserts ale and stops drivin g address on this risin g atclk ed g e. note that in a normal isa c y cle the host would keep ale hi g h. 6. for dma i/o read, the host tristates the mad[15:0] buff- ers. for dma i/o write, it drives the write data onto mad[15:0]. 7. host asserts cmd# s y nchronous to the fallin g ed g e of atclk to run the command and is re q uired to inhibit its ior#/iow# lines. 8. onl y cisa memor y devices can extend the c y cle with iochrdy. 9. dack# c y cle is minimum 1.5 atclk. host de-asserts cmd# s y nchronous to the risin g ed g e of atclk. ale atclk cmd# mad[15:0] (sd[15:0]) compact isa (cisa) dack# cycle operation 1. cisa host g ets address from the cpu address lines and b y te enable lines. the host then drives out a [ 23:10 ] +i/d#=0+m/io#=0 2 3 4 driven by host, tracked by cisa dma and memory devices iochrdy 5 address phase 1 d[15:0] address phase 2 1 ca[25:0] 6 sel#/atb# sel# possibly driven by cisa memory device 7 9 optionally driven by cisa memory device 8 appendix b page 232 912-3000-016 revision: 3.0 opti ? b.2.5 configuration cycle the cisa confi g uration c y cle is a special c y cle reserved for future expansion of cisa. the onl y confi g uration c y cle cur- rentl y defined is the broadcast c y cle; the onl y t y pe of broad- cast c y cle specified at this moment is the stop clock c y cle. the stop clock c y cle indicates that the host will immediatel y put the cisa peripheral devices into a low-power mode in which the y will no lon g er receive clocks. therefore, the cisa peripheral device must enter into a state in which it can as y n- chronousl y si g nal that it needs the clocks restarted. cisa devices mi g ht need to g enerate an interrupt back to the s y s- tem, which the y cannot do if not receivin g clocks. the mad[15:0] bit meanin g s for each phase of the stop clock confi g uration c y cle are shown below. in phase 1, the m/io# bit is alwa y s 1, and the i/d# bit is alwa y s 1, for an y confi g uration c y cle. brd is 1 to indicate a broadcast c y cle, and will alwa y s be zero for an y other confi g - uration c y cle. the stp# bit is 0 to indicate a stop clock c y cle, and will be 1 for all other c y cles. bits cc2:0 are the clock count bits that indicate to the cisa peripheral device how man y risin g clock ed g es to expect after cmd# g oes hi g h before the clock is actuall y stopped. the other bits of phase 1 are reserved and should not be decoded. in phase 2, isa# = 1 indicatin g that this will be a fast c y cle. sbhe# = 0 to indicate 16 bits of data. w/r# = 1 because the stop clock broadcast c y cle is alwa y s a write c y cle. the data phase of the stop clock c y cle contains no useful data and should not be latched. the g eneral structure of compact isa broadcast c y cles is shown in fi g ure b-5. table b-6 mad bits during stop clock configuration cycles phase mad15 mad14 mad13 mad12 mad11 mad10 mad9 mad8 mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 1 brd = 1 stp# = 0 cc2 cc1 cc0 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd i/d# = 1 m/io# = 1 2 same same same same same same same same same same same same same isa# = 1 sbhe# w/r# = 1 3 same same same same same same same same same same same same same same same same appendix b 912-3000-016 page 233 revision: 3.0 opti ? figure b-5 compact isa configuration cycle operation this example describes the broadcast confi g uration c y cle 1. cisa host initiates the confi g uration c y cle; it is not g en- erate form isa commands. the host drives out brd = 1 + i/d# = 1 + m/io# = 0 ( broadcast confi g uration c y cle ) . 2. cisa peripheral latches the command data on the risin g ed g e of atclk and decodes the information. 3. host drives out clock count, stop clock c y cle indicator, and remainin g command information on mad[15:0]. 4. host asserts ale. cisa devices latch clock count. cisa peripheral devices must not respond with sel#. 5. host asserts cmd# s y nchronous to the risin g ed g e of atclk to run the command. the broadcast confi g ura- tion c y cle is alwa y s zero wait states so it completes in one atclk. 6. after the host de-asserts cmd#, the cisa peripheral device is internall y in stprdy state. 7. after the number of clocks specified b y cc[2:0], the host stops the clock in its hi g h state. in the example, cc[2:0] = 001 ( the minimum allowed ) so the host will stop the clock on the next risin g atclk ed g e. each additional count re q uires the host to wait one more clock. 8. the cisa peripheral device is also countin g clocks while in stprdy state. on the specified atclk ed g e the device is in stpactv state. in stpactv state, the cisa peripheral device g ives sel#/atb# a third mean- in g : clkrun#. the device can assert clkrun# as y n- chronousl y at an y time while in this mode to g et the host to restart its clocks. 9. cisa peripheral device asserts clkrun# ( sel#/atb# ) on receipt of an interrupt to restart the clocks. 10. on next risin g atclk clock ed g e, cisa peripheral device de-asserts clkrun# ( sel#/atb# ) but must not drive it hi g h. device has left stprdy state but is still in stpactv state and cannot initiate or respond to an y c y cle. 11. on next fallin g atclk ed g e, the host drives sel#/atb# hi g h for ? atclk. 12. on next risin g atclk ed g e, the host stops drivin g sel#/ atb#. the cisa peripheral device leaves stpactv state on this clock ed g e and can either g enerate an inter- rupt driveback c y cle or can respond to c y cles from the host. ale atclk cmd# mad[15:0] (sd[15:0]) 2 3 4 driven by host stprdy 5 broadcast phase 1 broadcast phase 2 1 sel#/atb# driven by device 9 stpactv driven by host 10 11 12 6 7,8 appendix b page 234 912-3000-016 revision: 3.0 opti ? b.3 interrupt and dma request drive-back compact isa provides the si g nal sel#/atb# to g ive the cisa peripheral device limited ownership of the bus. the sel#/atb# si g nal acts as atb# ( at backoff ) when asserted with ale low. when the device asserts atb# to the host, the host inhibits further at bus operations and asserts the cmd# line to the cisa peripheral device to acknowled g e that the device now owns the bus. the peripheral device can onl y drive two t y pes of information onto the bus: interrupt re q uests and dma re q uests. fi g ure b-6 illustrates the s y nchronous irq/drq driveback c y cle. b.3.1 interrupt requests to drive interrupt re q uests, the cisa peripheral device drives the mad[15:0] lines low for each irq line it wishes to assert. the host side irq g eneration circuitr y samples atb# and cmd# active on the risin g atclk ed g e and latches the irq information on mad[15:0]. the irq g eneration circuitr y , whether external or built into the host, determines how to treat irq information. for pulse- t y pe interrupts it could latch the irqs and enable tristate buff- ers to drive the lines low for 1-3 atclks, for example. b.3.2 dma requests the cisa device must alwa y s precede the drq drive-back c y cle with an irq drive-back c y cle, even if no irqs have chan g ed state. to make dma re q uests, the cisa peripheral device drives the mad[15:8] lines low for each drq it wishes to chan g e. the device then sets the state of each mad[7:0] line to corre- spond to the drq state desired. the host side drq g enera- tion circuitr y samples atb# and cmd# active on the next risin g atclk ed g e after the ed g e on which irqs were sam- pled, and latches the drq information on mad[7:0] for the channels selected on mad[15:8]. the desired dma re q uest line states are latched b y the host and will remain in that state until cleared b y another drq drive-back c y cle. this scheme allows both dma sin g le trans- fer and dma block transfer modes to be used. the cisa peripheral device must assert sel#/atb# immediatel y an y time a drq line chan g es state ( assumin g the current c y cle is finished ) . the cisa host, in turn, must immediatel y deassert all drq inputs to its dma controller until the drive-back c y cle is complete. table b-7 irq/drq drive back cycle phase mad15 mad14 mad13 mad12 mad11 mad10 mad9 mad8 mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 irq irq15 irq14 irq13 irq12 irq11 irq10 irq9 irq8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 drq en7# en6# en5# rsvd en3# en2# en1# en0# drq7 drq6 drq5 rsvd drq3 drq2 drq1 drq0 appendix b 912-3000-016 page 235 revision: 3.0 opti ? figure b-6 compact isa interrupt and dma request drive-back cycle 1. cisa peripheral device must sample sel#/atb# and cmd# hi g h, and ale low, on two consecutive risin g ed g es of atclk. 2. cisa peripheral device asserts atb# on risin g ed g e of atclk to re q uest at backoff. if host was startin g a c y cle and was about to assert ale on the next fallin g ed g e of atclk, it must abort the c y cle and retr y it later. even if host is bus y and cannot respond to drive back re q uest immediatel y , it inhibits initiation of all i/o and dma oper- ations ( eoi to pci is blocked, for example ) . 3. as soon as at bus operations have been completed and bus is available, host drives mad[15:0] hi g h for ? atclk from a fallin g ed g e of atclk, then asserts cmd# after the net risin g ed g e of atclk. the host drives atb# low at this time. 4. cisa peripheral device ( s ) can drive interrupt data onto bus on next fallin g ed g e of atclk, drivin g low onl y those lines with irq activit y and not activel y drivin g hi g h the other lines. in this wa y , multiple cisa devices can drive the lines in parallel. 5. host irq g eneration circuitr y uses risin g ed g e of atclk, q ualified b y atb# and cmd# low, to latch irqs. the cisa device stops drivin g atb# at this time. the host controls atb# throu g hout the rest of the c y cle. 6. cisa peripheral device drives an y mad[15:-0] lines it was drivin g low hi g h for ? atclk, then tristates the lines for ? atclk. 7. cisa peripheral device drives drq information onto mad[7:0] and at the same time drives low the corre- spondin g lines mad[15:8] to indicate which drq chan- nels have a status chan g e to be transferred. 8. host drq g eneration circuitr y uses next risin g ed g e of atlck, q ualified b y atb# and cmd# low and previous irq c y cle, to latch drqs. the host drq g eneration cir- cuitr y ors the drqs with other s y stem drqs. 9. host de-asserts cmd# and atb# on risin g ed g e of atclk. b.4 performance control compact isa performance is comparable with that of 16-bit isa bus peripheral devices. in its simplest implementation, the cmd# si g nal is simpl y an and of mrd#, mwr#, ior#, and iow# from the standard at controller state machine. memory cycles are alwa y s assumed to be zero wait state . the cisa host detects a nows# command ever y time sel# is g enerated. the cisa peripheral device can use its iochrdy line to extend the c y cle and override the nows# status. all of this functionalit y is consistent with standard isa operation. i/o cycles cannot be made zero-wait-state c y cles on the isa bus, so b y default are not zero-wait-state c y cles on the cisa bus. however, performance improvement is possible if the cmd# duration is shortened to one atclk. future pcmcia i/o devices ma y be able to complete their c y cles this q uickl y , for example. for zero-wait-state cisa i/o operation, the c y cle timin g would have to chan g e from the standard isa tim- in g . the host can implement fast cisa timin g as an option. however, all cisa slave devices are required to be able to accept fast cisa timin g . fast cisa timing on the host side is defined as follows. if the cisa host is drivin g cmd# as derived from the lo g ical and of isa command lines ior#, iow#, mrd#, and mwr#, it sets isa# = 0 to indicate that the cisa peripheral device must assume isa timin g . if the host is capable of performin g fast cisa c y cles, it can set isa# = 1. in this case, the cisa peripheral device must deassert iochrdy earl y to len g then c y cles. sel#/atb# atclk cmd# mad[15:0] 1, 2 3 cmd# driven by host irq[15:0] 5 en#[7:0], drq[7:0] atb# driven by device 6 4 7 8 9 atb# driven by host atb# driven by both host and device appendix b page 236 912-3000-016 revision: 3.0 opti ? fast cisa timing on the device side is defined as follows. if the cisa host drives the isa# bit low, the cisa peripheral device assumes normal isa timin g for cmd# and iochrdy. if the cisa host drives isa# hi g h, the cisa peripheral device must drop iochrdy low immediatel y upon receivin g cmd# to len g then the c y cle; this is different from isa timin g . the cisa peripheral device will have a pro g rammable option to determine how iochrdy is deasserted. b y default, the device mi g ht drop iochrdy on ever y c y cle. for the example of a pcmcia controller on the cisa bus, onl y when a fast pcmcia card is inserted ( as indicated in the cis header of the card ) would card services be allowed to enable the fast cisa timin g option on the cisa peripheral device side. b.5 compatibility and host responsibilities compact isa does not interfere with standard isa operations or limit compatibilit y . this statement can be made with onl y the followin g restrictions: ? no device can drive the sd bus between isa c y cles. devices capable of drivin g the sd bus must sta y tristated at this time. ? atclk can be stopped onl y after a stop clock broadcast confi g uration c y cle. slower-than-standard clock speeds are allowed if interrupt latenc y is not an issue. ? isa bus masters cannot access cisa devices. standard isa masters are simpl y i g nored b y cisa devices since these masters cannot g enerate cmd# and so cannot run a cisa c y cle. isa bus masters can still take bus control and communicate with other isa peripherals. cisa interrupt latenc y ma y be an issue if a bus master prevents the cisa host from respondin g to atb# for an interrupt driveback c y cle. ? no cisa bus master capabilit y is currentl y defined. how- ever, the presence of the sel#/atb# si g nal and its at backoff feature leave open the possibilit y of future bus master capabilities. ? on receipt of an atb# re q uest, the cisa host must imme- diatel y inhibit all s y stem drq activit y ( possibl y b y deas- sertin g all drqs to the dma controller ) until the drive-back c y cle is complete. otherwise, unwanted dma c y cles could occur. b.6 shared speaker signal support (optional) compact isa provides a new scheme for the di g ital speaker output si g nal common to pcs and pcmcia controllers. this scheme allows all di g ital audio outputs to be tied to g ether without the xor lo g ic usuall y re q uired. the standard specification for the speaker data output is a si g nal driven in both the low-to-hi g h and hi g h-to-low direc- tions. the output cannot simpl y be respecified as open-col- lector, since there is no g uarantee that software will leave the speaker output line from the s y stem chipset in a hi g h or tristated condition. if it leaves the si g nal driven low, no other open-collector devices connected on the line could to gg le the si g nal. moreover, open collector outputs tend to consume excessive power. compact isa provides an efficient solution to the problem as described in the followin g sections. b.6.1 initial synchronization all cisa slave devices must tristate their spkr outputs at hard reset time and remain tristated until individuall y enabled. on the first ale g enerated b y the host, all participatin g cisa devices will s y nchronize to atclk and derive the si g nal atclk/2 that is in phase as shown in fi g ure b-7. four dis- tinct phases, 0 throu g h 3, are the result. cisa slave spkr outputs are still tristated at this point. figure b-7 synchronizing to atclk at 1st ale resetdrv at clk ale atclk/2 phase 0 phase 1 phase 2 phase 3 . . . appendix b 912-3000-016 page 237 revision: 3.0 opti ? b.6.2 spkr sharing during active mode the activities performed in each phase b y the cisa host and the cisa slaves are as g iven in table b-8. fi g ure b-8 illustrates the spkr handlin g re q uirements. figure b-8 shared spkrout signal management table b-8 spkr sharing during active mode phase slave host on the risin g atclk ed g e startin g phase 0 sample the state of spkr. sample the state of spkr. tristate spkr output. durin g phase 0: maintain spkr output tristated ( as it was from previous phase ) . maintain spkr output tristated. on the fallin g atclk ed g e startin g phase 1: sample di g ital audio source input. durin g phase 1: if di g ital audio source input sampled on atclk ed g e has chan g ed state since the previous phase 1 in which it was sampled, to gg le spkr. spkr is to gg led b y drivin g the opposite of the spkr value sampled in phase 0 onto the spkr output. on the risin g atclk ed g e startin g phase 2: tristate spkr output. tristate spkr output. sample the state of spkr. durin g phase 2: slave and host: maintain spkr output tristated. on the fallin g atclk ed g e startin g phase 3: no activit y on this ed g e. drive spkr pin to the value of spkr sam- pled in phase 2. durin g phase 3: maintain spkr output tristated ( as it was from previous phase ) . maintain spkr output driven. atclk/2 atclk phase 0: tri-state phase 1: toggle phase 2: tri-state phase 3: host drives current value phase 0: tri-state phase 1: toggle phase 2: tri-state phase 3: host drives current value audio source spkr device samples spkr to drive in phase 3 (all devices) device toggles spkr to reflect change in audio source device tri-states spkr because no toggle is needed device samples spkr to toggle in phase 1 appendix b page 238 912-3000-016 revision: 3.0 opti ? b.6.3 spkr sharing during stop clock mode durin g stop clock mode, cisa devices handle spkr as fol- lows. slave: tristate spkr. referrin g to fi g ure b-5, the exact period durin g which cisa slaves keep spkr tristated is defined as the period durin g which both stpactv and stprdy are hi g h. host: drive or tristate spkr. it is recommended that the host drive spkr low. note that even while cisa slave devices are in stop clock mode, the y must remain s y nchronized to the correct phase of atclk. the y do not res y nchronize on the next ale. b.6.4 audio output circuit recommendations the spkr output must never be connected directl y to a speaker or other low-impedance transducer. the shared spkr implementation depends on an r-c time constant lar g e enou g h that the si g nal will never chan g e its level an y appreciable amount across a period of 1.5 atclks, the max- imum number of clocks for which no device will be drivin g the spkr line. three atclks last for approximatel y 188ns. the r-c time constant of the desi g n must be si g nificantl y lar g er than this value. connectin g an 8 ohm speaker directl y would cause the line to be g in a transition when it was tristated. therefore, either capacitive couplin g or an amplifier circuit with a hi g h- impedance input is recommended. b.7 automatic voltage threshold detection compact isa devices are intended to work on either a tradi- tional 5.0v isa bus or on a local 3.3v isa bus. compact isa desi g ns are ver y power-conscious, so usin g external strap options on each cisa device to select the input buffer thresh- old ma y not be the best option. therefore, the compact isa host is re q uired to use the ale pin at reset to indicate the isa bus volta g e to cisa slaves. the correspondence is as follows. ? for a 5.0v isa bus, the host must assert the ale si g nal high when rstdrv g oes hi g h, and must keep it asserted for at least 1/2 atclk and at most 1 atclk after rst- drv g oes low. ? for a 3.3v isa bus, the host must keep the ale si g nal low when rstdrv g oes hi g h, and must maintain ale low for at least 1/2 atclk after rstdrv g oes low. this performance is required for cisa hosts, but cisa slave devices are not re q uired to use the feature. appendix c 912-3000-016 page 239 revision: 3.0 opti ? c. 82c602a notebook companion chip c.1 features c.1.1 general features the 82c602a, in 486 notebook mode, provides: ? multiplexers for interrupt and dma re q uest scannin g ?a b y te-wide latch or tristate buffer ? a decoder for dma acknowled g e si g nal g eneration ? an xd-sd bus buffer ? an rtc with cmos ram ? miscellaneous lo g ic. the attached circuit dia g ram illustrates the internal lo g ic of the notebook mode. c.1.2 power-saving features si g nals with tristate options are listed below. see the attached circuit dia g ram for a lo g ic representation of these tristate mechanisms. ?the si g nals sd[7:0] and xd[7:0] are tristated from a lo g ic combination of attris# ( pin 58 ) , romcs# ( pin 5 ) , romcs#/rtcd# ( pin 50 ) , and dwe#/kbdcs# ( pin 22 ) . ?the si g nals dack0-7#, kbdcs#, smemr#, and smemw# are tristated when the input si g nal attris# is low. ?the si g nals do0# and do0-7 are tristated when the input si g nal dtris# is low. all other si g nals are driven to their normal state, usuall y inac- tive. the power to the rtc can be disconnected durin g s y stem suspend mode even while the rest of the chip remains pow- ered. this feature results in extremel y low standb y power consumption and is described in the reducin g suspend power consumption section that follows. c.2 overview the notebook mode of the opti 82c602a chip provides g en- eral purpose multiplexers, latches, and lo g ic to anticipate future inte g rated s y stem desi g ns. this mode is enabled throu g h a strap option that operates as described below. c.2.1 modes/chipset support the 82c602a must follow the strappin g options show in table c-1. the 82c602a will sense the xd[7:0] bits durin g reset to determine which mode it will enter. in order to achieve a 0 value durin g reset, place a 4.7k w pull-down resistor on the appropriate xd line. in order to achieve a 1 value, no external are needed since the 82c602a contains internal pull-up resistors on the xd bus. the 82c602a is available b y default in a 100-pin pqfp ( plas- tic q uad flat pack ) . it is also available in a 100-pin tqfp ( thin q uad flat pack ) b y special order for all notebook modes. c.2.2 design notes the followin g information is important for proper incorporation of the 82c602a in s y stem desi g ns. 1. the 82c602a is a sin g le-volta g e part, usuall y selected as 5.0v. it has no provisions for 3.3v-to-5.0v translation. in most cases this limitation is unimportant, as the 82c602a is primaril y an isa bus interface device. how- ever, for implementations that provide 3.3v input si g nals, the desi g ner should be aware that 3.3v levels on 5.0v inputs draw excessive idle current ( on the order of 1ma per input ) . for example, the 373 latch buffer could be used to buffer ei g ht of the cpu address lines to the isa bus. however, when the s y stem is put into suspend mode, an y buffer inputs that remain at 3.3v will cause a current draw and create an undesirable situation for low power suspend mode operation. table c-1 mode strapping options note: all other strap combinations are reserved for desktop modes. mode/chipset supported xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 486 notebook mode/ 82C465MV 1 1 1 0 1 1 0 1 viper notebook mode a ( viper nba ) 11101110 viper notebook mode b ( viper nbb ) 11001110 appendix c page 240 912-3000-016 revision: 3.0 opti ? c.2.3 reducing suspend power consumption in its notebook modes, the 82c602a chip has been q ualified for operation at 3.3v. however, the internal rtc still re q uires 5.0v for proper operation. rtcvcc, pin 57, provides vcc to the rtc durin g active mode. the vbatt, pin 55, provides power onl y to maintain the rtc clock and cmos data durin g power down modes and is connected to a 2.4v-4.0v batter y . the rtcvcc pin supplies analo g circuit power to the rtc durin g run mode and must alwa y s be 5.0v, re g ardless of whether the rest of the chip is powered at 5.0v or 3.3v. to save power durin g low-power suspend mode ( when the rest of the chip is still powered ) , this pin ma y be disconnected from the suppl y volta g e. it is important that the suppl y be dis- connected, not simpl y brou g ht to g round. a p-channel mos- fet is ideal for this purpose. the g ate of the mosfet can be controlled b y ppwr0 or ppwr1 from the power control latch. for example, ppwr0 ma y be used to switch off rtcvcc b y usin g a p-channel mosfet as shown in fi g ure c-1. the auto-to gg le feature of the ppwr0 line must be enabled, syscfg 54h[0] = 0, and 68h[0] = 1. settin g bits syscfg 68h[3:2] = 10 provides the necessar y recover y time to the rtc analo g vcc. with this implementation, the mosfet will switch off the power of the analo g vcc onl y durin g suspend mode; the onl y current flow throu g h the analo g vcc is leak- a g e current ( less than 1 m a ) . figure c-1 rtcvcc switching circuit example the mosfet used for testin g at opti is a national? semi- conductor ndf0610, which has a t y pical g ate threshold volt- a g e of C2.4v ( C3.5v max / C1v min ) . c.2.4 82c602a power consumption measure- ments usin g the circuit of fi g ure c-1, the power consumption of the 82c602a notebook mode in use with the opti 82c463mv demonstration board is shown in the followin g two tables. table c-2 typical current consumption figures for rtc power table c-3 typical current consumption figures for digital power c.2.5 internal real-time clock (rtc) the internal rtc of the 82c602a is functionall y compatible with the ds1285/mc146818b. the followin g subsections will g ive detailed functional and re g ister features of the on-chip rtc of the 82c602a. c.2.5.1 rtc features ?s y stem wake-up capabilit y -- alarm interrupt output active in batter y backup mode ? 4.5v to 5.5v operation ? 114 b y tes of g eneral nonvolatile stora g e ? direct clock/calendar replacement for ibm ? at-compatible computers and other applications ? less than 1.0 m a load under batter y operation ? 14 b y tes for clock/calendar and control ? bcd or binar y format for clock and calendar data ? calendar in da y of the week, da y of the month, months, and y ears, with automatic leap- y ear ad j ustment ? time of da y in seconds, minutes, and hours - 12- or 24-hour format - optional da y li g ht savin g ad j ustment ? three individuall y maskable interrupt event fla g s: - periodic rates from 122 m s to 500ms -time-of-da y alarm once-per-second to-once-per-da y - end-of-clock update c y cle ppwr0 5.0v 14 41 49 71 91 57 82c602a 3.3v or 5.0v ndf0610 p-channel mosfet vcc rtcvcc parameter normal suspend analo g vcc < 1.5 m a~1 m a vbat ~1 m a~1 m a digital vcc = 3.3v digital vcc = 5v normal suspend normal suspend < 4ma < 30 m a < 4ma 250 m a appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 41 r e v i s i o n : 3 .0 opti ? c . 2 . 5.2 rtc ove r vi e w t h e o n - c hi p rt c i s a l o w - powe r m i c r op r oce s so r p e r i phe r al p r ov i d i n g a t i m e - of - day c l ock a nd 10 0 y ea r ca l en d ar w i t h a l a r m f eat u re s an d ba t te r y o per a t i on . th e rtc s u ppo r t s 3 . 3v s y s t ems . ot h e r rtc f ea t ure s i n c l ud e t h re e mask a b l e i n t e r- r up t s ou r ces , s q ua r e - w a ve ou t pu t , and 11 4 b y te s o f g ene r al n o nvo l a t i l e s t or a ge. wak e -up c apab i l i t y i s p r ov i de d b y an a l a r m i n t e r rup t, whi c h is a c t i ve i n bat t e r y bac k u p mo d e . the rtc wr i t e -p r o t ec t s th e c l o c k, c a le n da r , and s t o r a ge re g - i s te r s d ur i n g p o wer f a i l u r e . a b a cku p ba t te r y t hen ma i n t a i n s da t a a n d ope r at e s t h e c l oc k a n d c a l enda r . the on - ch i p rtc i s a f u l l y compa t i b l e r ea l - t ime c l ock f o r pc/ at- c ompa t ib l e c o mpu t er s and o th e r a p pl i c a t i on s . t h e on l y ex t e r n a l comp o nen t s a r e a 32 . 76 8 khz c ry s ta l and a ba c kup ba t te r y. c.2 . 5 . 3 rtc a d dres s map th e on - ch i p rtc p ro v id e s 1 4 b y t e s of c l oc k a n d c on t ro l / st a - t u s r e g i st e rs and 1 14 b y te s o f g en e ra l n o nvo l a t i l e st o rag e. f i g u r e c -1 ill u s t r a t e s t he a d d r e s s m a p f o r t h e r t c . fig u re c - 2 r t c a d d r ess m ap 0 c l o c k an d con t r ol st a tu s re g i s t e r s 00 14 b y t e s 13 0 0 14 s t o r a ge re g i s t e r s 0e 114 b y t e s 1 2 7 7f 0 secon d s 0 0 1 seco n ds ala r m 0 1 2 m i nu t es 02 3 m i nu t es a l arm 0 3 4 hou r s 04 bcd or b i n ar y fo r mat 5 hou r s a l a r m 0 5 6 d a y o f week 06 7 da t e o f mon t h 0 7 8 m on t h 0 8 9 y e a r 0 9 10 r e g i s t e r a 0 a 11 r e g i s t e r b 0 b 12 r e g i s t e r c 0 c 13 r e g i s t e r d 0 d appendix c page 242 912-3000-016 revision: 3.0 opti ? c.2.5.4 programming the rtc the time-of-da y , alarm, and calendar b y tes can be written in either the bcd or binar y format ( see table c-4 ) . these steps ma y be followed to pro g ram the time, alarm, and calendar: 1. modif y the contents of re g ister b: a. write a 1 to the uti bit to prevent transfers between rtc b y tes and user buffer. b. write the appropriate value to the data format ( df ) bit to select bcd or binar y format for all time, alarm, and calendar b y tes. c. write the appropriate value to the hour format ( hf ) bit. 2. write new values to all the time, alarm, and calendar locations. 3. clear the uti bit to allow update transfers. on the next update c y cle, the rtc updates all ten b y tes in the selected format. table c-4 time, alarm, and calendar formats address rtc bytes range decimal binary binary-coded decimal 0 seconds 0-59 00h-3bh 00h-59h 1 seconds alarm 0-59 00h-3bh 00h-59h 2 minutes 0-59 00h-3bh 00h-59h 3 minutes alarm 0-59 00h-3bh 00h-59h 4 hours, 12-hour format 1-12 01h-och am 81h-8ch pm 01h-12h am 82h-92h pm hours, 24-hour format 0-23 00h-17h 00h-23h 5 hours alarm, 12-hour format 1-12 01h-och am 81h-8ch pm 01h-12h am 82h-92h pm hours alarm, 24-hour format 0-23 00h-17h 00h-23h 6da y of week ( 1 = sunda y) 1-7 01h-07h 01h-07h 7da y of month 1-31 01h-1fh 01h-31h 8 month 1-12 01h-0ch 01h-12h 9 year 0-99 00h-63h 00h-99h appendix c 912-3000-016 page 243 revision: 3.0 opti ? c.2.5.5 square-wave output the rtc divides the 32.768khz oscillator fre q uenc y to pro- duce the 1hz update fre q uenc y for the clock and calendar. thirteen taps from the fre q uenc y divider are fed to a 16:1 multiplexer circuit. the output of this mux is fed to the sqw output and periodic interrupt g eneration circuitr y . the four least-si g nificant bits of re g ister a, rs[3:0], select amon g the 13 taps ( see table c-5 ) . c.2.5.6 interrupts the rtc allows three individuall y selected interrupt events to g enerate an interrupt re q uest. these three interrupt events are: 1. the periodic interrupt, pro g rammable to occur once ever y 122 s to 500ms. 2. the alarm interrupt, pro g rammable to occur once-per- second to once-per-da y , is active in batter y backup mode, providin g a wake-up feature. 3. the update-ended interrupt, which occurs at the end of each update c y cle. each of the three interrupt events is enabled b y an individual interrupt enable bit in re g ister b. when an event occurs, its event fla g bit in re g ister c is set. if the correspondin g event enable bit is also set, then an interrupt re q uest is g enerated. the interrupt re q uest fla g bit ( intf ) of re g ister c is set with ever y interrupt re q uest. readin g re g ister c clears all fla g bits, includin g intf, and makes int# hi g h-impedance. two methods can be used to process rtc interrupt events: 1. enable interrupt events and use the interrupt re q uest output to invoke an interrupt service routine. 2. do not enable the interrupts and use a pollin g routine to periodicall y check the status of the fla g bits. the individual interrupt sources are described in detail in the followin g subsections. table c-5 square-wave frequency/periodic interrupt rate register a bits square-wave periodic interrupt rs3 rs2 rs1 rs0 frequency units period units 0000 none none 0001 256 hz 3. 90625 ms 0010 128 hz 7.8125 ms 0011 8.192 khz 122.070 s 0100 4.096 khz 244.141 s 0101 2.048 khz 488.281 s 0110 1.024 khz 976.5625 s 0111 512 hz 1.953125 ms 1000 256 hz 3. 90625 ms 1001 128 hz 7.8125 ms 1010 64 hz 15.625 ms 1011 32 hz 31.25 ms 1100 16 hz 62.5 ms 1101 8 hz 125 ms 1110 4 hz 250 ms 1111 2 hz 500 ms ap p endix c p a g e 2 4 4 9 1 2 - 3 0 0 0 - 0 1 6 r e v i s i o n : 3 .0 opti ? pe r i odi c i nt e rr u pt t h e mu x ou t pu t use d t o d r i v e th e sqw o u tp u t a l s o dr i ve s t he i n t e r r up t g ene r a t io n c i r cu i t r y . i f t he pe r io d i c i n t e r r up t e ven t i s e n ab l ed b y w r i t i n g a 1 to t he per i od i c i n t e r r up t e n ab l e b i t ( pie ) in r eg i s t e r c , an i n t e r r u p t r e q u e s t is g ene r a t ed onc e e v er y 1 2 2 s t o 500ms . t h e p e r i o d be t wee n i n t e r r up t s i s s e l e c t ed b y t h e same b i t s i n reg i s t e r a t h at s e l e c t t h e s q ua r e-wa v e f r eque n cy ( s e e t ab l e c - 5 ) . se t t i ng osc[2 : 0 ] i n re g i s te r a t o 01 1 doe s no t af f e c t t he p e r i od i c i n t e r r up t t im i ng. a l arm in t e r rupt t h e al a rm i n te r r upt i s a c t i ve i n ba t t e r y b a cku p mo d e, p r ov i d- i n g a wa k e- u p ca p ab i l i t y . d u r i n g e a ch upd a te cy c l e, t he rtc comp a res t he hou r s, m i nut e s , an d s e cond s b y t e s w i t h t he t h ree co r r e spon d in g a l a r m by t e s . i f a m a t c h of a ll b y t e s i s f oun d , t he a l a r m in t e r ru p t e v en t f l a g b i t , a f i n r e g i s t er c , i s s e t to 1. i f t he al a rm e v en t i s e n ab l ed, a n i n t e r rup t r e q u e st is g e ne r ate d . an a l a r m b y te m ay be r e m o v ed f rom t h e compa r i s on by s e t- ti n g i t t o a d o n ' t c a re s t a t e. an a l a r m b yt e i s se t t o a don ' t c a r e s t a t e b y wr i t i n g a 1 to e a ch o f i t s t wo m o st s ig n i f i cant b i t s . a d o n ' t c a re s t a t e ma y be u sed t o se l e c t t he f re q uency o f a l arm in t e r ru p t eve n t s a s f o l low s : a. i f no n e o f t h e t h r ee a l arm b y t e s i s don ' t c a r e , t h e f re- q u enc y i s on c e pe r da y , wh e n ho u rs , m i nu t es , and s e c- o n ds m a t c h. b. i f on l y t h e h o ur a l arm by t e i s d on ' t ca r e , t h e f re q uency i s onc e p e r hou r w h e n m i nu t es and s e cond s ma t ch. c. i f on l y t he ho u r and m i nu t e a l a r m b y te s ar e do n ' t ca r e , t h e f r e q uen c y i s on c e p e r mi n u te whe n s e cond s ma t ch. d. i f t he ho u r , m i n u te , and s e co n d a l arm b y t e s a r e d o n ' t c a r e , t h e f r e q uenc y i s onc e p e r sec o nd. upda t e c y cl e i nt e rru p t the up d at e c yc l e en d ed f l a g b i t ( uf ) in r e g i s te r c i s s e t t o a 1 a t t h e e n d o f an u pda t e c yc l e . i f t he u pda t e i n t e r ru p t enab l e b i t ( u i e) o f reg i s t e r b i s 1 , a n d t h e upda t e t r ans f e r i nh i b i t b i t ( ut i ) in r eg i s t e r b is 0, the n an i n t e r r up t r eque s t i s g ene r - a t ed a t t h e e nd o f eac h u p da t e c y c l e. acces s ing rtc byt e s t i m e a nd ca l en d ar b y te s rea d dur i n g a n upda t e c y c l e m a y be i n e r ro r . th r ee meth o ds to ac c ess th e t ime and ca l en d ar b y t e s wi t ho u t amb i gu i t y a r e: 1. enab l e th e up d ate i n t e r r up t ev e n t t o gen e ra t e in t e r ru p t re q ues t s a t t he end o f t he u p da t e cy c le . th e in t e r ru p t hand l e r h a s a max i mum o f 9 9 9 m s t o a cce s s t h e cl o ck b y t e s b e fo r e t he ne x t up d at e cy c l e b e g i n s ( s ee f i g u r e c- 1 ). 2. po l l t h e u p da t e- i n - p r o g re s s b i t ( u i p ) in r e g i s t e r a . if u i p = 0 , th e po l l i n g r ou t i ne ha s a min i mum o f tbuc t ime t o acc e s s t h e c lo c k b y t e s ( s ee f ig u r e c - 1 ) . 3. us e t h e p e r i od i c i n t e r r up t e v en t t o g ene r a t e in t e r ru p t re q ues t s eve r y tp i t i m e, su c h tha t uip = 1 a lwa y s o ccu r s be t ween t he p e r i od i c i n t e r r up t s . the i n t e r rup t ha n d l er has a m i nimum of tp i / 2 + t bu c t ime to acce s s t he cl o ck b y t e s ( s ee fi g ure c - 1). f i g u re c - 3 u p date- e n d ed / p er i o d ic i nterr u pt re l ati o ns h ip t u c t b u c 1 s e c p ( tp i ) /2 ( t p i ) /2 tpi f f appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 45 r e v i s i o n : 3 .0 opti ? tc t i m e -bas e c r yst a l t h e rtc s t ime - bas e osc i l l a to r i s de s i g n ed t o wo r k w i th a n e x t e rna l p i e z oe l ec t r i c 3 2 . 7 68kh z cr y s t al . a cr y s t al c a n be r ep r ese n ted b y i t s e l ec t r i c a l eq u i v al e nt c i r cu i t a nd ass o c i at e d p a rame t e r s as sh o w n i n f i gu r e c-2 a n d t ab l e c-6 , re s pec- ti v e l y . l 1 , c1, an d r1 fo r m wh a t i s k nown a s t he mo t io n al a r m of t he c i r cu i t . c 0 i s th e sum o f t he ca p a c i t a nce b e twe e n e l ec- t r o des and t he ca p a c i ta n ce add e d b y th e l ea d s and moun t i n g s t r uc t ur e o f the c r y s t a l . th e eq u i v a l e nt i mpedan c e o f t h e c r y s t a l v a r i es w ith t h e f r e q u enc y o f o sc i l la t i on. t h ere a r e two f re q uenc i e s a t wh i ch t h e c ry s t a l i m p edan c e a p pea r s p u re l y r es i s t i ve ( x e = 0 ) . t h e y r e i nd i ca t ed b y t w o p o i n ts o n t he g ra p h , know n as t h e se r i e s r e son a nt (f s ) a n d a n t i - r es o nan t ( f a ) f r eq ue n c i es . osc i l l a to r s o per a t i ng th e c r y s- t a l a t t h e re s onan t f r e quen c y ( f s ) a r e t erme d se r i es r es o nant c i r cu i t s, w h ere a s t hos e tha t op e ra t e t he c r y s ta l a r oun d f a a r e t e r m e d pa r a l l e l r e s o nan t . the o n -c h i p rtc us e s a p a r a l l el r e so n an t o s c i l l a t or c i r cu i t . the f r e qu e ncy o f o s c i l l a t i on in t h is mod e l i es b e twe e n f s and f a and i s d i c t a t ed by t he e ff ec t i v e l oa d c apac i t anc e a ppea r i n g ac r oss t he c r ys t a l i n pu t s, as e x p l ai n ed nex t . t a ble c-6 crystal p a r ameters f i g u r e c - 4 q u a r t z c r ys t a l e q u i v a l e n t c i r c u i t par a m e t e r symbol va l ue un i t nom i n al f r e q ue n cy f 3 2 . 7 6 8 k h z load cap a c i tan c e c l 6 p f mot i on a l i n duc t ance l 1 907 6 .66 h mot i on a l capa c i t ance c1 2 .6 x 10 - 3 p f mot i on a l res i s t ance r1 27 kohm shun t c a pac i t ance c0 1 . 1 pf r1 l1 c1 c0 r e x e ap p endix c p a g e 2 4 6 9 1 2 - 3 0 0 0 - 0 1 6 r e v i s i o n : 3 .0 opti ? rtc osc i l l a t or t h e p a ra l l e l r e sona n t r t c os c i ll a t o r c i rc u i t i s comp r is e d o f a n i n v e r t i n g m i c r o- p ower amp l i f i er w i th a pi - t y pe fe e dbac k n e t- wo r k . f i gu r e c - 4 i l l u s t r a t e s a bl o ck d i a g ram o f t he o sc il la t or c i r cu i t w i th t he c r y st a l as pa r t o f t he pi - fe e dbac k n e two r k . t h e o s c i l l a t o r c i r cu i t e n su r es th a t t h e cr y st a l i s ope r a t in g in t he p a ra l l e l r e so n anc e r e gi o n o f t h e i mped a nc e cu r ve. t h e a c t u al f re q u enc y a t w h ic h t h e c i rc u i t w il l os c i ll a t e d e pend s o n t h e l oa d ca p a c i t a nce , c l . th i s pa r ame t er i s t h e d y nam i c ca p a c i ta n ce o f t h e t o ta l c i r cu i t a s measu r ed o r com- p u te d a c ro s s t h e c r y s t a l t e r min a l s . a pa r a l l e l r e so n an t c r y s t a l l i ke t h e d t - 2 6 is c a li b r a t e d at t h i s l oa d u s i n g a pa r a l l e l o s c i l l a t or c i r cu i t . c l i s c o m p ut e d f r om c l 1 a nd c l 2 as g i v en be l ow: c l = (c l 1 * c l 2 ) / ( c l 1 + (c l 2 ) t h e r t c s c l 1 a n d c l 2 va l ues a r e t r immed t o pro v i d e a p pr o x i m a t e l y a l oad c a pac i t ance ( c l ) o f 6p f a cr o s s c r y s t al t e r m i na l s . t h i s i s t o m a tc h t he s pec i f ie d l oa d capa c i t an c e ( 6p f ) a t wh i c h t he r e commended dt - 26 cr y s t a l is c a li b r a t e d to r e so n a t e a t t h e nomi n al f re q uenc y o f 32 . 768 k hz . re f e r r i n g to t h e impe d ance g r ap h o f f i g u r e c-3 , a i nd i ca t e s t he po i n t o f re s onan c e wh e n c l e q u a l s t h e spec i f i e d l oa d cap a c i ta n ce o f t h e c r y s t a l. f i g ure c-6 i m p ed a nc e gr a ph fig u re c - 4 r t c o sci l lator circ u i t b l o ck d i a g ram 400 0 000 350 0 000 300 0 000 250 0 000 200 0 000 150 0 000 100 0 000 50 0 000 0 - 50 0 000 327 60 327 66 327 62 327 64 327 68 327 70 327 72 327 74 327 76 327 78 327 80 f l a fa f r equ e n c y at c l = 6 pf f r e quen c y at c l = 4 p f f r e q uen c y ( h z) r e ac t a nc e ( o h m s ) ( b ) d e ta i l ed a r e a of p a r a l l e l re s o n an c e 50m vdd 2 1 8 2 c602a rtc x1 x2 c l2 c l1 6pf d t - 2 6 appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 47 r e v i s i o n : 3 .0 opti ? t i me k e epi n g ac c u ra c y t h e a ccu r a c y o f t h e f r e q u enc y o f osc i l la t i on depe n ds on: ? c r y s t a l f r e q uen c y to l e r ance ? c r y s t a l f r e q uen c y s t a b i li t y ? c r y s t a l a g i n g ? e f f e c t iv e l oa d c a pac i t a nc e i n o s c i l l a t o r c i r cu i t ? b o a r d l a y out c r ys t al f r equen c y tol e ran c e . th e f r e quen c y t o le r an c e p a r ame t e r i s t he ma x i mum f r e q uen c y de v i a t i on f r om t h e n o m i na l f r e qu e ncy ( in t h i s case 32 . 76 8 khz ) a t a spec i f i e d t e mpe r a t ure , e x pre s sed in ppm ( p a r ts p er m il l i o n ) o f nom i nal f r e q uen c y . i n t h e case o f t h e g r ade a dt - 26 c r y s t a l , t his p a rame t e r i s 2 0 p p m a t 2 5 c. c r ys t al fre q uency sta b i l i t y . th i s pa r amete r , de p enden t o n t he a n g l e a n d t y pe o f c u t , i s de f in e d a s th e max i mum f re- q u enc y dev i a t i on f rom th e nom i na l f r eq u ency ove r a spec i f i e d t e mpe r a t ure r a n g e , e x pr e sse d i n p p m o r pe r ce n tag e o f n o m i - n a l f re q u ency . f i g u r e c - 5 show s a ty p i c a l c u r ve o f fr e q uen c y va r i at i on w i t h t empe r a t ure f or t h e kds dt - 26 c r y s t al. c r ys t al ag i ng . as a c r y s t a l a g es , some f r eq u ency s h i f t m a y b e o bse r ved . dr i f t w i th a g e i s s pec i f i ed t o be ty p i ca l l y 4 ppm f o r t h e fi r st y e a r a n d 2 ppm pe r yea r f o r t he l i f e o f t h e kds dt - 26 c r y s t a l . l o ad cap a ci t anc e . f o r a pa r a l l e l re s onan t c a l ib r a t ed c r y s t a l, t he c r y s ta l man u fa c tu r e r spe c i f i e s t he l oa d capa c i t an c e at wh i ch t he c r y s ta l w il l pa r a l l e l r e sona t e a t t he n o min a l f r e - quen c y . f r om t h e g ra p h o f fi g ure c- 6 , in c re a s i ng t h e e f fe c - t i ve l o a d c a pac i t ance b y h a ng i n g a d d i t i ona l c apac i t or s on e i t h er of t h e x 1 o r t h e x 2 p i n w i l l e f f e c t i v e l y l o we r t h e res o - nan t f r e quen c y p o in t a t o war d fs . t he d e v i at i o n o f t he f r e - quen c y fl w i th l oad cap a c i ta n ce i s g i v e n b y: f l = f s ( 1 + c1 / 2 (c0 + c l )) whe r e c 1 i s t h e crys t a l mo t i ona l c apac i t anc e an d c 0 i s t h e c r y s t a l sh u n t s t ra y ca p a c i t a nce , a s e x pl a in e d a b ove . c l is t h e e f fe c t i ve l oad capa c i t an c e a cr o ss t h e c r y s ta l i n put s . a l l ow i n g f o r c apa c i t anc e du e t o b o ar d l ayou t t r a ce s l e ad i ng to t h e x 1 and x2 p i ns , th e rtc i s t r i m m e d in t e r na l l y t o p r ov i de an e f f e c t i ve l oa d ca p a c i ta n ce o f l e s s t ha n 6pf . con n ec t i n g a 6pf c r y s t a l d i r e ct l y t o t h e x1 a nd x 2 p i n s w i l l c aus e t h e cl o ck t o o s c i l l a t e app r ox i mat e l y 2 4 p p m f a s t e r t ha n t h e nom i na l f r e - quen c y of 32 . 768 k hz , f o r r easo n e x pl a in e d p re v io u s l y. fo r max i m u m accu r ac y , i t i s r e commende d t h at a sma l l t r im cap a c i to r ( < 8 p f) be h o oked t o t he x2 p i n t o mo v e th e res o - nan t po i nt c l os e r t o t he nom i na l f r e quen c y . t he g rap h o f fi g - ur e c- 6 sh o ws t he v a r i a t i on o f f r e quen c y w i t h add i t i o na l l oad cap a c i tan c e o n t he x2 p i n o f t h e rtc. tr a n s l at i n g t h e da t a i n f ig u re c - 6 i n t o a pr a c t i c al r u l e o f t h u m b : fo r e ve r y a d di t i ona l 1 .5 4 pf c apac i t anc e o n th e x 2 pi n , t h e f r e q u ency wi ll dec r ea s e b y 0. 8 h z o r a d f / f o f - 24 . 4 ppm ar o und 82 . 768 k h z . fig u r e c - 7 t ypical t emp e rature c h aracte r i stics - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 -2 6 -2 2 -3 0 -1 8 -1 4 -1 0 -6 -2 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 10 ap p endix c p a g e 2 4 8 9 1 2 - 3 0 0 0 - 0 1 6 r e v i s i o n : 3 .0 opti ? fig u re c - 8 f req u e n c y v a r i ation v ers u s l o ad cap a c i ta n c e bo a rd layou t . gi v en the hi gh i n put i m p edan c e o f the cry s t al i np u t pi n s x 1 an d x2 , c a re sho u l d b e t a ke n to r o ut e h i gh- s peed sw i tc h in g s i g na l t r ace s away f r om t hem . pr e fe r ab l y a g r ou n d-p l an e l ay e r s hou l d b e u sed ar o und th e c r y s t a l a rea t o i so l a t e cap a c i t i ve - cou p l i n g o f h ig h f r e q uen c y s i g na l s . t h e t r a c e s f r om t h e c r y s t a l l eads t o t h e x1 and x 2 p in s m u st b e k ep t sho r t w i t h mi n ima l be n ds . a good r u l e o f t humb i s t o k eep th e c r y s ta l t r ace s w i t h i n 5mm o f t h e x 1 a n d x 2 p i ns. f i na l l y , a 0. 1 f c e ram i c by p ass c apac i t or s h ou l d be p l ac e d c lo s e t o t he vcc p i n o f t he rt c to pro v i d e an i mp r ove d sup- p l y i nt o t h e c l ock os c i l la t o r sta r t - up . ba r r i n g a ccu r ac y i s sue s , t h e r t c wi l l o s c i l l a t e wi t h a n y 32 . 768 k h z c r y s ta l . when ho o ked to t he x1 a n d x2 p i ns i n ce r t ai n con f i g ur a t i ons , howe v er , pa s s i ve com- p o nen t s can l ead to os c i ll a t o r s t ar t - up pro b lem s : ? e x c e s s i ve l o a d i n g o n t h e cr y s t al i npu t p in s x 1 a n d x2 ? u s e o f a r es i s t i ve fe e dbac k e l eme n t ac r oss t he cr y st a l. va l u e s a bov e 10 p f o n e i t he r t h e x1 o r x 2 pi n mus t be a v o i ded . th e f e edba c k e l emen t i s bu i l d i n to t h e rtc f o r s t a r t- u p a n d n o r e s i s t i v e fe e dbac k e x te r na l to t he p a r t is r e qu i r e d. os c i l la t o r con t rol whe n powe r i s f i r s t app li ed t o t he r t c and vc c i s abo v e v p f d , t h e i n te r na l osc il l a to r and f r e quenc y di v i d e r a r e t u rn e d o n b y wr i t i n g a 010 pa t te r n to b i ts 4 t h r o ug h 6 of reg i s t e r a . a pa t te r n o f 0 11 be h ave s as 0 10 bu t a d di t i ona l l y t r a n s f o r m s re g i s t er c i n to a r e ad / w r i t e re g i s t e r. t h is a ll o w s t h e 32 . 768 k h z o u tp u t on t h e s q u a re - wave p i n t o b e t u r ned on . a p a t t e rn o f 11 x t u r n s t h e o s c ill a t o r o n , bu t k eep s t h e f r e que n cy d i v i der d i s ab l ed . any o t he r pa t te r n t o t hese b i t s k e eps t h e o sc ill a t o r o f f. c.2 . 5 . 7 power - down / power - up c y cle th e rtc s p o w e r - up / powe r -d o wn c y c l es ar e d i f f e r en t . the rtc con t i nuou s l y m o ni t o r s vcc f or o u t - of - t ol e ran c e . d u r i ng a powe r f a i l u re , w h e n vcc f a l l s b e l o w v p f d ( 2 . 5 3v t y p i ca l ) , t h e rtc wr i t e- p ro t ec t s th e c l o c k a nd st o ra g e r e g i s t e r s. t h e powe r sou r ce i s sw i t ched t o bc when vcc i s l e ss t han v p f d and b c i s g r ea t er t h an v p f d , or whe n vcc i s l es s t han v bc and v b c is l e s s t h an v p f d . rtc op e ra t i on an d s t or a ge da t a ar e sus t a i ne d b y a v a l i d back u p ene r gy sou r ce . when vcc i s abo v e v p f d , th e powe r sou r c e is vcc. wr i t e- p ro t ec t i on c o n- t i nu e s f o r t c s r t i m e a f t e r vcc r i s e s abo v e v p f d . the rt c co n t i nuo u s l y mon i t or s vcc f o r ou t - o f - to l e r anc e . dur i n g a powe r f a i l ure , when vc c f a l l s be l ow v p f d ( 4 . 17v t y pi c a l ) , t h e rtc wr i t e- p ro t ec t s t he c lo c k an d s t ora g e r e g i s - t e rs . whe n vcc i s be l ow v b c ( 3v t y p i ca l ) , t he p o wer sou r ce i s sw i t c hed t o bc . rtc o per a t i on a nd s to r a g e dat a a r e su s - t a in e d b y a va l i d bac k up en e rg y sou r ce . when vcc i s a b ove v b c , t he powe r s o ur c e i s vcc. w r i t e - pr o te c t i on con t i nues f o r t c s r t i me af t e r vcc r i se s a b ove v p f d . - 300 - 200 - 100 0 100 200 300 400 500 600 0. 4 2 0. 8 4 0 1. 2 6 1. 6 8 2. 1 2. 6 2 2. 9 4 3. 3 6 3. 7 8 4. 2 4. 6 2 5. 0 4 5. 4 6 5. 8 8 6. 3 6. 7 2 7. 1 4 7. 5 6 7. 9 8 8. 4 8. 8 2 appendix c 912-3000-016 page 249 revision: 3.0 opti ? c.2.5.8 control/status registers the four control/status re g isters of the rtc are accessible re g ardless of the status of the update c y cle ( see table c-7 ) . register a re g ister a pro g rams the fre q uenc y of the periodic event rate, and oscillator operation. re g ister a provides the status of the update c y cle. see table c-8 for re g ister as format. register b re g ister b enables the update c y cle transfer operation, s q uare-wave output-interrupt events, and da y li g ht savin g ad j ustment. re g ister b selects the clock and calendar data formats. see table c-8 for re g ister bs format. register c re g ister c is a read-onl y event status re g ister. see table c-8 for re g ister cs format. register d re g ister d is a read-onl y data inte g rit y status re g ister. see table c-8 for re g ister ds format. table c-7 control/status registers summary notes: na = not affected 1. except bit 7 2. read/write onl y when osc[2:0] in re g ister a is 011 ( binar y) . reg loc (hex) read write bit name and state on reset 7 (msb) 6 5 4 3 2 1 0 (lsb) a0ayes yes 1 uip na osc2 na osc1 0 osc0 0 rs3 na rs2 na rs1 na rs0 na b 0b yes yes uti na pie 0 aie 0 uie 0 sqwe 0 df na hf na dse na c0cyes no 2 intf 0 pf 0 af 0 uf 0 - 0 32ke 0 - 0 - 0 d0dyesnovrtna-0-0-0- 0-0-0-0 table c-8 registers a through d bit formats 76543210 0ah register a uip (ro) update-in- progress: 1 = an rtc update cycle may be in progress. uip is cleared at end of each update cycle. this bit is also cleared when the uti bit in register b = 1. osc[2:0] oscillator control bits 2 through 0: controls state of oscillator and divider stages. 010 = enables rtc operation by turning on oscilla- tor and enabling frequency divider (rtc begins its first update after 500ms) 11x = turns oscillator on, but keeps frequency divider disabled rs[3:0] rate select bits 3 through 0: these bits select one of the 13 frequencies for the sqw output and the periodic interrupt rate, as shown in table c-4 appendix c page 250 912-3000-016 revision: 3.0 opti ? 0bh register b uti update trans- fer inhibit: inhibits the transfer of rtc bytes to the user buffer. 0 = allows transfer 1 = inhibits transfer and clears uie pie periodic inter- rupt enable: allows an inter- rupt request due to a peri- odic interrupt event. 0 = disable 1 = enable aie alarm interrupt enable: allows an inter- rupt request due to an alarm interrupt event. 0 = disable 1 = enable uie update cycle interrupt enable: allows an inter- rupt request due to an update ended interrupt event. 0 = disable 1 = enable this bit is auto- matically cleared when the uti bit = 1. sqwe square-wave enable: enables square-wave output. 0 = disable and hold low 1 = enable df data format: selects numeric format in which the time, alarm, and calendar bytes are repre- sented. 0 = bcd 1 = binary hf hour format: selects the time-of-day and alarm hour for- mat. 0 = 12-hour format 1 = 24-hour format dse daylight saving enable: allows daylight saving time adjustments. 0 = disable 1 = enable ( 1 ) (1) on the last sunday in october, the first time the rtc increments past 1:59:59 am, the time falls back to 1:00:00 am. on the first sunday in april, the time springs forward from 2:00:00 am to 3:00:00 am. 0ch register c intf interrupt request flag: this flag is set to a 1 when any of the fol- lowing is true; aie & af = 11 pie & pf = 11 uie & uf = 11 reading regis- ter c clears this bit. pf periodic event flag: this bit is set to a 1 every tpi time, where tpi is the time period selected by the settings of rs[3:0] in register a. reading regis- ter c clears this bit. af alarm event flag: this bit is set to a 1 when an alarm event occurs. reading regis- ter c clears this bit. uf update event flag: this bit is set to a 1 at the end of the update cycle. reading regis- ter c clears this bit. nu not used: these bits are always set to 0. 0dh register d vrt (ro) valid ram and time: 0 = backup energy source is depleted ( 1 ) 1 = valid backup energy source nu (ro) not used: these bits are always set to 0. (1) when the backup energy source is depleted (vrt = 0), data integrity of the rtc and storage registers is not guaranteed. table c-8 registers a through d bit formats (cont.) 76543210 appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 51 r e v i s i o n : 3 .0 opti ? c.3 si g nal d e fin i ti o ns fig u re c - 9 4 8 6 nb m o d e pin d i a g ram (100-p i n p q fp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sd1 sd0 gnd a e n rs t drv do 0 # s m e m w # s m e m r# drq5 vcc a t cyc# m e m w # m e mr# k b dcs# gnd dac k 7 # dac k 6 # dac k 5 # dac k 3 # dac k 2 # dac k 1 # dac k 0 # a t tri s # r t c _ 5 v ir q 8 # v b att x t a l out x t a l i n gnd ir q 1 5 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 drq7 d a ck m ux0 gnd d a ck m ux1 d a ck m ux2 di1 di0 ir q 1 4 ir q 1 2 ir q 1 0 ir q 7 ir q 6 ir q 4 vcc gnd i o r# i o w# rqmx3 rqmx2 rtcas k b c l k dwe # /k b dcs# r s t# kbc l k2 rqmx0 nc rqmx1 gnd di7 di6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 di 5 di 4 di 3 di 2 do0 do1 do2 do3 do4 gnd vcc do5 do6 do7 ir q 3 ir q 1 dt ri s # rom c s # la t c h rom c s# / r t cd# drq6 drq3 drq1 xd7 xd6 xd5 xd4 xd3 xd2 vcc gnd xd1 xd0 drq0 sd7 sd6 sd5 sd4 sd3 sd2 8 2 c60 2 a 4 8 6 nb m o de ap p endix c p a g e 2 5 2 9 1 2 - 3 0 0 0 - 0 1 6 r e v i s i o n : 3 .0 opti ? fig u re c -10 4 8 6 nb m o d e pin d i a g ram (100-p i n t q f p) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 do 0 # s m e m w # s m e m r# drq5 vcc a t cyc# m e m w # m e mr# k b dcs# gnd dac k 7 # dac k 6 # dac k 5 # dac k 3 # dac k 2 # dac k 1 # dac k 0 # a t tri s # r t c _ 5 v ir q 8 # v b att x t a l out x t a l i n gnd ir q 1 5 drq7 d a ck m ux0 gnd d a ck m ux1 d a ck m ux2 di1 di0 i r q 1 4 i r q 1 2 i r q 1 0 ir q 7 ir q 6 ir q 4 vcc gnd i o r# i o w # rqmx3 rqmx2 rtcas k b c l k dwe # /k b dcs# r s t# kbc l k2 rqmx0 82c6 0 2a 4 86 nb mode 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc rqm x 1 gnd di 7 di 6 di 5 di 4 di 3 di 2 do0 do1 do2 do3 do4 gnd vcc do5 do6 do7 ir q 3 ir q 1 dt ri s # rom c s # la t c h r o m c s# /r tc d # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 rst drv aen gnd sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 drq0 xd0 xd1 gnd vcc xd2 xd3 xd4 xd5 xd6 xd7 drq1 drq3 drq6 appendix c 912-3000-016 page 253 revision: 3.0 opti ? table c-9 486 nb mode - numerical pin cross-reference list pin # pin name pin type 1 drq7 i 2dackmux0 i 3gnd g 4dackmux1 i 5dackmux2 i 6di1 i 7di0 i 8irq14 i 9irq12 i 10 irq10 i 11 irq7 i 12 irq6 i 13 irq4 i 14 vcc p 15 gnd g 16 ior# i 17 iow# i 18 rqmx3 o 19 rqmx2 o 20 rtcas i 21 kbclk i 22 dwe#/kbdcs# i 23 rst# i 24 kbclk2 i 25 rqmx0 o 26 nc 27 rqmx1 o 28 gnd g 29 di7 i 30 di6 i 31 di5 i 32 di4 i 33 di3 i 34 di2 i 35 do0 o 36 do1 o 37 do2 o 38 do3 o 39 do4 o 40 gnd g 41 vcc p 42 do5 o 43 do6 o 44 do7 o 45 irq3 i 46 irq1 i 47 dtris# i 48 romcs# i 49 latch i 50 romcs#/rtcd# i pin # pin name pin type 51 irq15 i 52 gnd g 53 xtalin i 54 xtalout o 55 vbatt i 56 irq8# o 57 rtc_5v i 58 attris# i 59 dack0# o 60 dack1# o 61 dack2# o 62 dack3# o 63 dack5# o 64 dack6# o 65 dack7# o 66 gnd g 67 kbdcs# o 68 memr# i 69 memw# i 70 atcyc# i 71 vcc p 72 drq5 i 73 smemr# o 74 smemw# o 75 do0# o pin #pin name pin type 76 rstdrv o 77 aen o 78 gnd g 79 sd0 i/o 80 sd1 i/o 81 sd2 i/o 82 sd3 i/o 83 sd4 i/o 84 sd5 i/o 85 sd6 i/o 86 sd7 i/o 87 drq0 i 88 xd0 i/o 89 xd1 i/o 90 gnd g 91 vcc p 92 xd2 i/o 93 xd3 i/o 94 xd4 i/o 95 xd5 i/o 96 xd6 i/o 97 xd7 i/o 98 drq1 i 99 drq3 i 100 drq6 i pin #pin name pin type table e-1 486 nb mode - alphabetical pin cross-reference list pin name pin # pin type aen 77 o atcyc# 70 i attris# 58 i dack0# 59 o dack1# 60 o dack2# 61 o dack3# 62 o dack5# 63 o dack6# 64 o dack7# 65 o dackmux0 2 i dackmux1 4 i dackmux2 5 i di0 7 i di1 6 i di2 34 i di3 33 i di4 32 i di5 31 i di6 30 i di7 29 i do0# 75 o do0 35 o do1 36 o do2 37 o do3 38 o do4 39 o do5 42 o do6 43 o do7 44 o drq0 87 i drq1 98 i drq3 99 i drq5 72 i drq6 100 i drq7 1 i dtris# 47 i dwe#/kbdcs# 22 i gnd 3 g gnd 15 g gnd 28 g gnd 40 g gnd 52 g gnd 66 g gnd 78 g gnd 90 g ior# 16 i iow# 17 i irq1 46 i irq3 45 i pin name pin # pin type irq4 13 i irq6 12 i irq7 11 i irq8# 56 o irq10 10 i irq12 9 i irq14 8 i irq15 51 i kbclk 21 i kbclk2 24 i kbdcs# 67 o latch 49 i memr# 68 i memw# 69 i nc 26 romcs# 48 i romcs#/rtcd# 50 i rqmx0 25 o rqmx1 27 o rqmx2 19 o rqmx3 18 o rtcas 20 i rst# 23 i rstdrv 76 o rtc_5v 57 i pin name pin # pin type sd0 79 i/o sd1 80 i/o sd2 81 i/o sd3 82 i/o sd4 83 i/o sd5 84 i/o sd6 85 i/o sd7 86 i/o smemr# 73 o smemw# 74 o vbatt 55 i vcc 14 p vcc 41 p vcc 71 p vcc 91 p xtalin 53 i xtalout 54 o xd0 88 i/o xd1 89 i/o xd2 92 i/o xd3 93 i/o xd4 94 i/o xd5 95 i/o xd6 96 i/o xd7 97 i/o pin name pin # pin type appendix c page 254 912-3000-016 revision: 3.0 opti ? c.3.1 486 nb mode signal descriptions refer to the 486 nb internal circuitr y schematic in section 4.0 for complete details. c.3.1.1 clock and reset interface signals c.3.1.2 interrupt/control interface signals c.3.1.3 isa dma arbiter interface signals signal name pin no. signal type (drive) signal description rst# 23 i-s reset: reset input to the 82c602a lo g ic. rstdrv 76 o ( 24ma ) reset drive: inverted rst#. signal name pin no. signal type (drive) signal description irq1, irq3, irq4, irq6, irq7 46, 45, 13, 12, 11 i interrupt request bits 1, 3, 4, 6, and 7 irq10, irq12, irq14, irq15 10, 9, 8, 51 i interrupt request bits 10, 12, 14, and 15 ior# 16 i i/o read iow# 17 i i/o write memr# 68 i memory read memw# 69 i memory write smemr# 73 o ( 24ma ) smemr# with tristate control smemw# 74 o ( 24ma ) smemw# with tristate control signal name pin no. signal type (drive) signal description drq[7:5] drq3, drq1, drq0 1, 100, 72, 99, 98, 87 i dma request bits 7 through 5, 3, 1, and 0 dack[7:5]#, dack[3:0]# 65:63, 62:59 o ( 6ma ) dma acknowledge bits 7 through 5, and 3 through 0 dackmux[2:0] 5, 4, 2 i encoded dacks rqmx3 18 o ( 6ma ) mux of drq1, drq3, drq6, and drq7 rqmx2 19 o ( 6ma ) mux of irq10, irq15, and drq5 appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 55 r e v i s i o n : 3 .0 opti ? c . 3 . 1.4 bu s i nt e r f ac e sig n als c . 3 . 1.5 r e al - t i m e c l ock and keyboa r d i n t er f ace s i gna l s rqmx1 27 o ( 4ma) mux of irq4, irq6, irq8#, and irq12 rqmx0 25 o ( 4ma) mux of irq1, irq3, irq7, and irq14 dwe# / kbdcs# 22 i dram write enable or keyboard chip select s i gna l n a m e p i n n o . s i gnal (dr i ve) type s i gna l d e scr i p t ion d i [ 7 :0] 2 9 :34 , 6 , 7 i data buffer inputs 7 through 0 do [ 7: 0 ] 4 4:4 2 , 39 : 35 o ( 4ma) data buffer outputs 7 through 0 do0# 75 o ( 8ma) inverted data buffer output 0 dtr i s# 47 i data buffer tristate control: when active, will tristate the data buffer. romcs# 48 i rom chip select: this sig na l , whe n ac t i ve , w i l l a l l o w rom o n t h e xd b u s to p u t i n fo r ma t io n o n t h e sd b u s. romcs# / rtcd# 50 i rom chip select and rtc command line: this sig n a l i s used t o e n ab l e a c ces s es t o t he r o m and rtc f r om t he 82c4 6 5mv. s d [ 7 : 0 ] 8 6 : 7 9 i / o ( 2 4 m a) sd bus lines 7 through 0 x d [ 7 : 0 ] 9 7 : 9 2, 8 9 , 8 8 i / o ( 6ma) xd bus data lines 7 through 0: xd4 and xd1 must be sampled low during r e se t to en t e r t he 486 no t eboo k mod e . a 2 . 2k pu l l -dow n r e s i s t or i s re c o m- men d ed o n t he s e l i nes . a l l x d l in e s i n t h e 8 2 c602 a hav e i n t e r n al wea k pu l l -u p r es i s t o r s a nd d o n o t r e q u i re an y e x te r na l pu l l - u p r e si s t o rs. at t ris# 58 i tristates at bus outputs: this is used to tristate the isa bus during l o w p o wer mode. atcyc 70 i at cycle indication s i gna l n a m e p i n n o . s i gnal (dr i ve) type s i gna l d e scr i p t ion rtcas 20 i real-time clock address strobe: rtcas is used to demultiplex the address/ d a ta bu s . the f a l li n g edge o f as l a t c hes t h e a ddr e ss on xd[7 : 0 ] . rtc _ 5v 57 i real-time clock 5.0v: this pin must be connected to +5v during no r ma l ope r - a t i on . a s s o on as th i s i npu t d r op s b e low 4 . 0v , t he rtc/cmos ram i s p ro- t ec t ed f r om w r i te a c ces s es ( r ead acc e sse s w il l a l so be b l ocke d ). vbatt 55 i voltage battery: this pin is connected to the cmos and rtc battery. s i gna l n a m e p i n n o . s i gnal type (dr i ve) s i gna l d e scr i p t ion appendix c page 256 912-3000-016 revision: 3.0 opti ? c.3.1.6 miscellaneous interface signals c.3.1.7 power and ground pins irq8# 56 o interrupt request bit 8: the alarm output interrupt g enerated b y the internal rtc. xtalin 53 i crystal oscillator input: 32.768khz xtal input. xtalout 54 o crystal oscillator output: 32.768khz xtal output. kbclk 21 i keyboard clock: this input is used for demuxin g interrupts and dma re q uests. kbclk2 24 i keyboard clock / 2: this input is used for demuxin g interrupts and dma re q uests. kbdcs# 67 o ( 6ma ) kbdcs# qualified with aen: allows the s y stem to access the ke y board con- troller. signal name pin no. signal type signal description nc 26 no connection: this pin should be left unconnected. latch 49 i data buffer latch: this si g nal controls the latchin g of information on the data bus. aen 77 i address enable: this input is used to ensure that the s y stem has access to the real-time clock. signal name pin no. signal type signal description vcc 14, 41, 71, 91 p power connection gnd 3, 15, 28, 40, 52, 66, 78, 90 g ground connection le g end: g ground i/o input/output gground od open drain i/o input/output p power sch schmitt-tri gg er signal name pin no. signal (drive) type signal description appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 57 r e v i s i o n : 3 .0 opti ? c.4 s c h em a tics f i g u r e c- 1 sh o ws a s chema t i c o f th e i n t e rn a l c i r c u i t r y fo r t he 82c6 0 2 a w h en in t he 486 not e book mode. fig u re c -11 8 2 c602a i n tern a l c i r cuitry i n 486 n o teb o ok m o de ap p endix c p a g e 2 5 8 9 1 2 - 3 0 0 0 - 0 1 6 r e v i s i o n : 3 .0 opti ? c.5 8 2c602a m ec h ani c al p ack a ge o u tli n e t h e 8 2c602 a i s a va i l a bl e i n a 1 00- p i n tqf p by spe c i a l o r de r f o r a l l no t eb o ok m o des ; d e f a ul t pac k a g i n g is 1 0 0 - p in p q f p fig u re c - 1 2 8 2 c602a 100-p i n plastic q uad f l at pack ( p q fp) appen d ix c 9 1 2 - 3 0 0 0 - 0 16 p a ge 2 59 r e v i s i o n : 3 .0 opti ? fig u re c - 13 8 2 c602a 100- p i n t hin q u ad p ack (tq f p ) appendix c page 260 912-3000-016 revision: 3.0 opti ? the information contained within this document is subject to chan g e without notice. opti inc. reserves the ri g ht to make chan g es in this manual at any time as well as in the products it describes, at any time without notice or obli g ation. opti inc. assumes no responsibility for any errors contained within. in no event will opti inc. be liable for any dama g es, direct, indirect, incidental or consequential resultin g from any error, defect, or omission in this specification. copyri g ht ? 1997 by opti inc. all ri g hts reserved. opti is a trademark of opti incorporated. all other brand and product names are trademarks or copyri g hts of their respective owners. opti inc. 888 tasman drive milpitas, ca 95035 (408) 486-8000 sales information opti ? headquarters: opti inc. 888 tasman drive milpitas, ca 95035 tel: 408-486-8000 fax: 408-486-8011 sales offices: japan opti japan kk murata buildin g 6f, 2-22-7 ohhashi me g uro-ku tokyo 153, japan tel: 81-3-5454-0178 fax: 81-3-5454-0168 taiwan opti inc. 9f, no 303, sec 4, hsin yih road taipei, taiwan, roc tel: 886-2-325-8520 fax: 886-2-325-6520 united kingdom & europe opti inc. 30 windmill avenue bicester, oxon ox6 7dy u.k. tel: + 44-1-869-369-161 fax: same united states opti inc. 4400 n. federal hi g hway, ste. #120 boca raton, fl 33431 tel: 561-395-4555 fax: 561-395-4554 opti inc. 20405 state hi g hway 249, ste. #220 houston, tx 77070 tel: 281-257-1856 fax: 281-257-1825 representatives: united states alabama/mississippi concord component reps 190 line quarry rd., ste. #102 madison, al 35758 tel: 205-772-8883 fax: 205-772-8262 florida engineered solutions ind., inc. 1000 e. atlantic blvd., ste. #202 pompano beach, fl 33060 tel: 305-784-0078 fax: 305-781-7722 georgia concord component reps 6825 jimmy carter blvd., ste. #1303 norcross, ga 30071 tel: 770-416-9597 fax: 770-441-0790 illinois micro-tex, inc. 1870 north roselle rd., ste. #107 schaumbur g , il 60195-3100 tel: 708-885-8200 fax: 708-885-8210 massachusetts s-j associates, inc. 267 boston road corporate place, ste. #3 n. billerica, ma 01862 tel: 508-670-8899 fax: 508-670-8711 michigan jay marketing 44752 helm street., ste. a plymouth, mi 48170 tel: 313-459-1200 fax: 313-459-1697 new jersey s-j associates, inc. 131-d gaither dr. mt. laurel, nj 08054 tel: 609-866-1234 fax: 609-866-8627 new york s-j associates, inc. 265 sunrise hi g hway rockville centre, ny 11570 tel: 516-536-4242 fax: 516-536-9638 s-j associates, inc. 735 victor-pittsford victor, ny 14564 tel: 716-924-1720 north & south carolina concord component reps 10608 dunhill terrace ralei g h, nc 27615 tel: 919-846-3441 fax: 919-846-3401 ohio/w. pennsylvania lyons corp. 4812 fredrick rd., ste. #101 dayton, oh 45414 tel: 513-278-0714 fax: 513-278-3609 lyons corp. 4615 w. streetsboro richfield, oh 44286 tel: 216-659-9224 fax: 216-659-9227 lyons corp. 248 n. state st. westerville, oh 43081 tel: 614-895-1447 fax: same texas axxis technology marketing, inc. 701 brazos, suite 500 austin, tx 78701 tel: 512-320-9130 fax: 512-320-5730 axxis technology marketing, inc. 6804 ashmont drive plano, tx 75023 tel: 214-491-3577 fax: 214-491-2508 virginia s-j associates, inc. 900 s. washin g ton st., ste. #307 falls church, va 22046 tel: 703-533-2233 fax: 703-533-2236 wisconsin micro-tex, inc. 22660 broadway, ste. #4a waukesha, wi 53186 tel: 414-542-5352 fax: 414-542-7934 international australia braemac pty. ltd. unit 6, 111 moore st., leichhardt sydney, 2040 australia tel: 61-2-550-6600 fax: 61-2-550-6377 china legend electronic components. ltd. unit 413, hon g kon g industrial technolo g y centre 72 tat chee avenue kowloon ton g , hon g kon g tel: 852-2776-7708 fax: 852-2652-2301 france tekelec airtronic, france 5, rue carle vernet 92315 sevres cedex france tel: 33-1-46-23-24-25 fax: 33-1-45-07-21-91 germany kamaka rheinsrasse 22 76870 kandel germany tel: 49-7275-958211 fax: 49-7275-958220 india spectra innovation unit s-822 manipal centre 47 dickenson road ban g alore 560-042 kamataka, india tel: 91-80-558-8323/3977 fax: 91-80-558-6872 israel ralco components (1994) ltd. 11 benyamini st. 67443 tel aviv israel tel: 972-3-6954126 fax: 972-3-6951743 korea woo young tech co., ltd. 5th floor koami bld g 13-31 yoido-don g youn g duen g po-ku seoul, korea 150-010 tel: 02-369-7099 fax: 02-369-7091 singapore instep microsolutions pte ltd. 18, tannery lane, #05-02 lian ton g buildin g sin g apore 347780 tel: 65-741-7507 fax: 65-741-1478 south america uniao digital rua guido caloi bloco b, piso 3 sao paulo-sp, cep 05802-140 brazil tel: 55-11-5514-3355 fax: 55-11-5514-1088 switzerland datacomp ag silbernstrasse 10 8953 dietikon switzerland tel: 41-1-740-5140 fax: 41-1-741-3423 united kingdom spectrum 2 gran g e mews, station road launton, bicester oxfordshire,ox6 0dx uk tel: 44-1869-325174 fax: 44-1869-325175 mmd 3 bennet court, bennet road readin g berkshire, rg2 0qx uk tel: 44 1734 313232 fax: 44 1734 313255 (5/97) opti inc. 888 tasman drive milpitas, ca 95035 tel: (408) 486-8000 fax: (408) 486-8001 www: http://www.opti.com/ |
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